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March 2012

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Subject:
From:
"Gumpert, Ben" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Gumpert, Ben
Date:
Wed, 21 Mar 2012 19:30:18 +0000
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Bill,

I see the confusion; 610 mentions a target condition for cracks, but then doesn't follow up with an acceptable or defect condition for cracks. 

But later in the document, a solder mask scratch that bridges non-common circuits is indicated as a defect for all classes, so I would have to say a crack bridging non-common circuits is also a defect for all classes.

Ben

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of William Clark
Sent: Wednesday, March 21, 2012 3:03 PM
To: [log in to unmask]
Subject: EXTERNAL: [TN] Acceptability of Cracked Solder Mask

It is not clear to me from IPC 610-E if a crack in a solder mask constitutes a Class 1 or Class 2 defect.  Pictures of the typical cracks we are seeing are at the link below.  The crack in picture 3 repeats at the same feature on every board in the array.  The cracks were not visible on the bare board and the boards passed the tape test.  I'm looking for input on the suitability of these boards.

Thanks

Bill

http://s1066.photobucket.com/albums/u408/clarkerg/

 

Bill Clark

Manufacturing Engineering and Quality Manager

ERG, <http://www.ergpower.com/>   Inc.  2601 Wayne Street, Endicott, NY
13760

607-754-9187

 



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