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From:
Dwight Mattix <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Dwight Mattix <[log in to unmask]>
Date:
Wed, 14 Mar 2012 09:49:23 -0700
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yes, small enough hole and soldermask right up to 
the hole (don't pull it back -- leave it 1:1) on the backside can work fine.

long ago, far away (Phil Bavaro and I -- but 
mostly Phil :-))  worked this out on some 
programs before Phil went elsewhere.  At the time 
we tried to standardarize our notes but ran into 
resistance from some SMT Mfg Eng's and would have 
constant stream of questions and confusion from 
PWB suppliers about the s/m requirements. Ergo, 
we went to the epoxy fill as a concession to the 
madness that ensued with the "simpler" approach.

No note is ever perfect. Typically they reflect 
the work of a committee with sometimes conflicting agendas and biases:

For what it's worth and YMMV (your mileage may 
vary): It's free and I'd love to hear suggestions 
for improvement, correction or caution.

HOLES INDICATED TO BE 100% EPOXY FILLED AFTER 
PLATING AND BEFORE FINAL SURFACE FINISH.
EPOXY FILL SHALL BE PLANAR(-0.001/+0.00O) AND NOT PROTRUDE FROM THE HOLES.
USE 100% SOLIDS NON-CONDUCTIVE EPOXY (SAN-EI 
PHP-900 IR-10F, Taiyo THP-100DX-1 or <OEM 
CUSTOMER NAME REDACTED> APPROVED EQUIVALENT).

At 09:09 AM 3/14/2012, Frank Kimmey wrote:
>Jack, Via farms will be a nightmare until you 
>work out the bugs. You need to figure out the 
>density, diameter, aspect ratio, etc. We use 
>lots of them and have worked over the numbers 
>enough to find small enough vias so as not to 
>have solder flow through issues but acceptable 
>plating. This is the one time I really 
>appreciate lead free (doesn't flow as freely as 
>SnPb). As George stated there is a combination 
>of hole size and stencil development you will 
>need to go through with your assembly to 
>optimize the process enough to make it all good. 
>My suggestion would be to avoid fill and use 
>size and stencil if you can on high layer count 
>or extreme temp boards. Unless you get a real 
>good CTE match, risk of delam is a definite 
>consideration. Talk to you assembler and 
>fabricator prior to the design, see where they 
>can help you. Good luck, FNK Frank N Kimmey CID+ 
>Manager ­ PCB Design Powerwave Technologiess 
>Inc. Mobile ­ 916-670-0645 -----Original 
>Message------ From: TechNet 
>[mailto:[log in to unmask]] On Behalf Of Jack Olson 
>Sent: Wednesday, March 14, 2012 6:54 AM To: 
>[log in to unmask] Subject: Re: [TN] Purpose of 
>these plated vias? I have to add via farms to a 
>design TODAY for the first time ever. Which part 
>of your post is the "bad idea?" Should I call 
>out some kind of via fill or leave them open? 
>Would it help to design the paste screen 
>windowpane pattern to avoid all the vias? (paste 
>between them, in other words?) Jack (aka "the 
>new guy") On Wed, 14 Mar 2012 06:35:26 -0700, 
>Dwight Mattix <[log in to unmask]> wrote: >we 
>build boards with thermal via farms (usually 
>under PA's,sometimes >power devices) everyday. 
>Rather than deal with the solderign issues 
>we >have them filled with non-conductive epoxy 
>and planarized. >Typically a Peters or Taiyo 
>material and San-Ei if it needs to 
>be >overplated (bad idea but sometimes 
>specified). Click the following link to report 
>this email as 
>spam: 
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