Jack,
Via farms will be a nightmare until you work out the bugs.
You need to figure out the density, diameter, aspect ratio, etc.
We use lots of them and have worked over the numbers enough to find small enough vias so as not to have solder flow through issues but acceptable plating.
This is the one time I really appreciate lead free (doesn't flow as freely as SnPb).
As George stated there is a combination of hole size and stencil development you will need to go through with your assembly to optimize the process enough to make it all good.
My suggestion would be to avoid fill and use size and stencil if you can on high layer count or extreme temp boards.
Unless you get a real good CTE match, risk of delam is a definite consideration.
Talk to you assembler and fabricator prior to the design, see where they can help you.
Good luck,
FNK

Frank N Kimmey CID+
Manager – PCB Design
Powerwave Technologies Inc.
Mobile – 916-670-0645

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jack Olson
Sent: Wednesday, March 14, 2012 6:54 AM
To: [log in to unmask]
Subject: Re: [TN] Purpose of these plated vias?

I have to add via farms to a design TODAY for the first time ever.
Which part of your post is the "bad idea?"
Should I call out some kind of via fill or leave them open?
Would it help to design the paste screen windowpane pattern to avoid all the vias?
(paste between them, in other words?)

Jack (aka "the new guy")

On Wed, 14 Mar 2012 06:35:26 -0700, Dwight Mattix <[log in to unmask]> wrote:

>we build boards with thermal via farms (usually under PA's,sometimes 
>power devices) everyday. Rather than deal with the solderign issues we 
>have them filled with non-conductive epoxy and planarized.
>Typically a Peters or Taiyo material and San-Ei if it needs to be 
>overplated (bad idea but sometimes specified).


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