The overplating of vias in a thermal via farm is a bad idea. We've 
seen a lot more incidence of delam when doing it that way. It was a 
frequent issue when using older more expansive (obsolete) fill 
materials with higher volatile content (not saying CB100 but you do 
the math). It's not as big an issue with the newer fills that have 
closer CTE match to the pwb.  Still, capping the vias gives the fill 
something to press upward on in unison. It can overcome the outlayer 
adhesion to the underlying laminate and blister. Put that many vias 
in close proximity and it makes a pretty good ram.

I'm sure I've pix around here but it's older issue. Changed our 
design rule and it's died down as an issue. As a rule only overplated 
filled vias now where theres a socket or probe contact required on the via.


At 06:53 AM 3/14/2012, Jack Olson wrote:
>I have to add via farms to a design TODAY for the first time ever.
>Which part of your post is the "bad idea?"
>Should I call out some kind of via fill or leave them open?
>Would it help to design the paste screen windowpane pattern to avoid 
>all the vias?
>(paste between them, in other words?)
>
>Jack (aka "the new guy")
>
>On Wed, 14 Mar 2012 06:35:26 -0700, Dwight Mattix 
><[log in to unmask]> wrote:
>
> >we build boards with thermal via farms (usually under PA's,sometimes
> >power devices) everyday. Rather than deal with the solderign issues
> >we have them filled with non-conductive epoxy and planarized.
> >Typically a Peters or Taiyo material and San-Ei if it needs to be
> >overplated (bad idea but sometimes specified).


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