Wayne,

I've always read that coverage requirement the same way you do.
Your void is not a defect.

Ben

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Knapp, Wayne B
Sent: Tuesday, March 13, 2012 4:54 PM
To: [log in to unmask]
Subject: EXTERNAL: [TN] Conformal Coating Void.

Dear TechNetters,

I have a circuit board in final inspection with a small void (1/16" dia.) in the conformal coating. Other than this one small void, the rest of the board has good, even coverage and no electrical conducting surfaces are exposed. The void is in an area with solder mask. There is an electrical trace underneath, but the solder mask is not disturbed. Based on my interpretation of J-STD-001D, Sec. 10.1.2.2 (See below), I don't see a violation of this requirement. Can someone weigh in and let me know if I'm interpreting the standard correctly.

10.1.2.2 Coating Coverage Conformal coating shall:
* Be free of cracks, crazing, voids, bubbles, mealing, peeling, wrinkles or foreign material which expose component conductors, printed circuit conductors, (including ground planes) or other conductors and/or violates design electrical clearance.
Thanks in advance,
Wayne




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