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March 2012

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Wed, 14 Mar 2012 08:53:40 -0500
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TechNet E-Mail Forum <[log in to unmask]>, Jack Olson <[log in to unmask]>
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Jack Olson <[log in to unmask]>
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I have to add via farms to a design TODAY for the first time ever.
Which part of your post is the "bad idea?"
Should I call out some kind of via fill or leave them open?
Would it help to design the paste screen windowpane pattern to avoid all the vias?
(paste between them, in other words?)

Jack (aka "the new guy")

On Wed, 14 Mar 2012 06:35:26 -0700, Dwight Mattix <[log in to unmask]> wrote:

>we build boards with thermal via farms (usually under PA's,sometimes
>power devices) everyday. Rather than deal with the solderign issues
>we have them filled with non-conductive epoxy and planarized.
>Typically a Peters or Taiyo material and San-Ei if it needs to be
>overplated (bad idea but sometimes specified).

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