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December 2011

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From:
"Stadem, Richard D." <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Stadem, Richard D.
Date:
Tue, 13 Dec 2011 16:12:54 -0600
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Yes. Dave brings up many good additional points, just as I knew he would! :)
Here at GD, and I know the same is true of many other high-rel OEMs, we strongly discourage the use of QFN package types. Even if they can be soldered in such a way to overcome the issues Dave and I discussed, there often remains the issue of delta CTEs. With such small  and short solder joints (remember that H affects the modulus of elasticity directly) the packages have been known to fail after far fewer thermal cycles than their compliant-leaded counterparts.

From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Tuesday, December 13, 2011 3:53 PM
To: TechNet E-Mail Forum; Stadem, Richard D.
Cc: [log in to unmask]
Subject: Re: [TN] TI Paste Recommendations


Hi folks -- one more comment to add to Richard's good information is that the center pad on a QFN is the primary feature for controlling surface tension influences for the component. If you use too much solder paste you can cause solder joint wetting/alignment defects of the smaller outer pads. Additionally, the amount of solder paste and the specific pattern you use on the center pad has a large influence on how many voids you end up with in the center pad solder joint.  QFNs are a neat component technology but have some specific assembly demands that we didn't have before their introduction on designs.

Dave Hillman
Rockwell Collins
[log in to unmask]


"Stadem, Richard D." <[log in to unmask]>
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12/13/2011 03:01 PM
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Re: [TN] TI Paste Recommendations







QFNs are very typically subjected to an aperture reduction. Usually the peripheral pads are reduced by 10-15%, and if a large belly pad is present, the stencil aperture reduction is typically between 40% to 60% of the pad area.

To understand why, think of it like this:
A chip capacitor, resistor, or a leaded SOIC, QFP, etc. all have someplace for the molten solder to flow other than the pad itself. Chips have endcap terminations, molten solder can wet out to the edges of the pads and run up the sides of these endcap terminations. Likewise with leaded components. In all of these cases, the solder has somewhere to go; there is no real constraint that would cause the surface energy of the molten solder to go "out of bounds" in the form of solder spattering.

In the case of QFNs, if you print solder paste in a one-to-one ratio with the pads, the molten solder has no place to wet and flow. With the component body mass sitting on the resultant puddles or blobs of molten solder on the belly pad and the peripheral pads as well, spattering occurs, and that is why there are so many solder fines trapped under the QFN part. To prevent this, the stencil aperture is reduced such that the smaller amount of solder has someplace to flow.


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Joyce Koo
Sent: Tuesday, December 13, 2011 2:40 PM
To: [log in to unmask]
Subject: Re: [TN] TI Paste Recommendations

For QFN, 7093 is the guideline you want.  QFN is rather different compare to the BGAs.

Joyce Koo
Materials Researcher - Materials Interconnect Lab
Research In Motion Limited
Office: (519) 888-7465 79945
Mobile: (226) 220-4760

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Gerald Bogert
Sent: Tuesday, December 13, 2011 3:28 PM
To: [log in to unmask]
Subject: Re: [TN] TI Paste Recommendations

December 13, 2011

Solder paste size can depend on the part manufacturer recommendations.  For example, Freescale for their BGA P013 processor recommends that the PC board solder pad and stencil aperture diameters should generally be the same; a 1 to 1 ratio.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of William Noel
Sent: Tuesday, December 13, 2011 2:52 PM
To: [log in to unmask]
Subject: [TN] TI Paste Recommendations

Hello all - I am working on creating a 24 pin QFN footprint for my CAD library.  Is there a valid reason for making the solder paste smaller than the actual pad outline?  I notice that TI consistently seems to recommend a smaller paste outline than pad outline.  Additionally, they recommend a series of small square paste squares to appear on the thermal pad rather than a single smaller square of paste.  Essentially, IPC-7351 recommendations are different than the TI recommendations.  Any help?  Thank you.

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