Steve,

You're bang on the money with that one, it's caught us out before now;
these components are a real pain!

Regards,
	Iain

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Steve Gregory
Sent: 07 October 2011 01:44
To: [log in to unmask]
Subject: Re: [TN] [DC] QFN layout


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IMHO, I wouldn't have silkscreen anywhere in the footprint.

As for following manufacturers guidelines, sometimes you can get led
down a path that just doesn't work. I followed the manufacturers
guidelines for my stencil on a 3-row QFN to the letter one time, stencil
thickness that they recommended, and including the checker board pattern
they recommended for the thermal pad. The part teeter-tottered on the
thermal pad with bridges on one side and opens on the other. After
progressively tweeking things (two stencils later) I finally had one
that worked...

Sometimes these parts just get thrown over the wall and it's your
problem to figure out how to put 'em on the boards.

Steve

-----Original Message-----
From: Jack Olson
Sent: Thursday, October 06, 2011 3:46 PM
To: [log in to unmask]
Subject: Re: [DC] QFN layout

I just searched IPC-7093 (Design and Assembly Process Implementation for
Bottom Termination Components) and was surprised to discover that there
isn't a single mention of silkscreen. Maybe we dropped the ball on that
one...

As far as I know, voids aren't an issue for the thermal pad, but of
course they are for solder joint if they are causing opens or
intermittent connections. You might try posting this on the IPC TechNet
forum, there are a lot of assemblers there who might have some insight
on your situation.
http://ipc.org/ContentPage.aspx?pageid=TechNet-E-mail-Forum

best wishes,
Jack

.
On Thu, Oct 6, 2011 at 9:24 AM, Arlene Fox
<[log in to unmask]>wrote:

> Heather,
>
> All of the major IC manufacturers have Application notes available 
> with design guidelines for their QFN packages. I've found these Ap 
> notes to be extremely helpful as they provide recommendations not only

> for the pcb footprint but also for stencil design.
> We've successfully placed many QFN packages of all sizes using these 
> notes.
>
> Good luck
> Arlene Fox, CID
> Enercon Technologies
>
> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of 
> Heather Gregg
> Sent: Wednesday, October 05, 2011 9:39 PM
> To: [log in to unmask]
> Subject: [DC] QFN layout
>
> Dear Designer Council,
> I have recently joined a company which is having great difficulty with

> soldering on a QFN part. The main trouble is solder voids under the 
> component leads, resulting in opens or intermittent operation. One 
> thing I noticed is that this particular layout has a silkscreen 
> outline under the part, between the lead lands and the thermal land. I

> would think silkscreen under a QFN would be a bad idea. What is the 
> prevailing wisdom regarding this in the layout world?
>
> Thank you,
> Heather Gregg
>
>
>


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