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August 2011

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Subject:
From:
Dave Schaefer <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Dave Schaefer <[log in to unmask]>
Date:
Fri, 19 Aug 2011 09:23:42 -0500
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Follow the Electrical Spacing requirements of IPC2221 Table 6.1 providing they are not less than the values specified by IPC2222 Section 9.1.3 for Clearance Area in Planes.

Vias and other thru padstacks should be constructed to conform to IPC2222 9.1.3 Class 3 if your application is military / aerospace. And as others have stated, don't mess with reducing or removing unused pads during design - if you need vias within the split area have them abide by the standard power layer antipads and clearances of the above specifications.

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