At 09:54 AM 6/7/2011, Chris Mahanna wrote:
>Victor,
>
>As an independent lab running these two methods
>side-by-side for about 3 years now, I can tell
>you there is very little user-side risk to
>switching to 2.6.27. There is however,
>substantial relative risk to staying with 2.6.8 (or wave, as you ask).
>With respect to soldering thermal excursion
>induced failures, the 80/20 rule always
>boils-down to barrel cracks and post sep.
True for more conventional PTH
stackups. However, if it's heavy on sequential
lam, buried via and stacked uVia then delamination is a major concern.
>In general, 2.6.8 does not induce barrel cracks,
>regardless of # of cycles, while 2.6.27 is
>surprisingly good at it. We have not seen a
>2.6.27 induced crack be classified as a false non-conformance.
>Of course you can parlay this into 2.6.27 +
>2.6.7.2 (as PCQRR has for years), just be sure
>to define the number of 2.6.27 cycles!
>
>On the other hand, 2.6.27 does induce
>post-sep. You just have to be ready with the
>competence and fortitude to call a less-ugly separation.
>
>My suggestion is to move to 2.6.27 as soon as
>feasible. IMO, do not paint yourself in a
>corner by forcing the stress of entire
>parts. 2.6.27 tolerances were designed for
>coupons! It is sometimes physically impossible
>to get an entire part to meet the profile in
>forced convection, regardless of the oven.
>
>An aerospace prime recently released a drawing
>note of minimum excision size (not sure I should
>say what the size is) for DPA work against
>2.6.27. I see this as very reasonable and a
>likely winner in the industry debate on the
>issue. To my knowledge, such excisions have
>always been acceptable for 2.6.8 work.
>
>Hope this helps.
>
>Chris
>
>Chris Mahanna
>Robisan Lab
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Victor Hernandez
>Sent: Tuesday, June 07, 2011 11:35 AM
>To: [log in to unmask]
>Subject: [TN] PCB/PWB - Thermal Stress - Solder Float - TM650, 2.6.8
>
>Fellow TechNetters:
>
> I apologize for multiple post of this
> inquiry. I have had no feedback on and would
> definitely like to have some sort of dialogue on the topic.
>
>Victor,
>
>-----Original Message-----
>From: Hernandez, Victor G
>Sent: Monday, June 06, 2011 2:14 PM
>To: Joyce Koo
>Cc: Hernandez, Victor G
>Subject: FW: PWB - Thermal Stress - TM650, 2.6.8
>
>Joyce,
>
> Any thoughts on this scenario.
>
>Victor,
>
>-----Original Message-----
>From: Hernandez, Victor G
>Sent: Monday, June 06, 2011 12:24 PM
>To: TechNet E-Mail Forum
>Cc: Hernandez, Victor G
>Subject: PWB - Thermal Stress - TM650, 2.6.8
>
>Fellow TechNetters:
>
> How valid would it be to send an entire
> board, 16X19x0.094 inches, through the wave
> solder process x number of times, 1x, 2x, 3x,
> etc., and call it thermal stress. Also the
> extracted coupon size are ¾ x 1/2 inches
> removed with a router . What are the Pros and
> Cons with this method of thermal stress in accordance with IPC guidelines.
>
>"X"
>
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