Since I got named, feel like obligated to reply ;-). Cisco got a good paper at year's ECTC conference (May 31 to June 3, 2011) "Effects of Multiple Rework on the reliability of lead-free BGA assembly", by Hongtao Ma, et.al. You might be able to get a copy from IEEE. (sorry no paper from my side, copyright issue). Good luck.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Victor Hernandez
Sent: Tuesday, June 07, 2011 11:35 AM
To: [log in to unmask]
Subject: [TN] PCB/PWB - Thermal Stress - Solder Float - TM650, 2.6.8
Fellow TechNetters:
I apologize for multiple post of this inquiry. I have had no feedback on and would definitely like to have some sort of dialogue on the topic.
Victor,
-----Original Message-----
From: Hernandez, Victor G
Sent: Monday, June 06, 2011 2:14 PM
To: Joyce Koo
Cc: Hernandez, Victor G
Subject: FW: PWB - Thermal Stress - TM650, 2.6.8
Joyce,
Any thoughts on this scenario.
Victor,
-----Original Message-----
From: Hernandez, Victor G
Sent: Monday, June 06, 2011 12:24 PM
To: TechNet E-Mail Forum
Cc: Hernandez, Victor G
Subject: PWB - Thermal Stress - TM650, 2.6.8
Fellow TechNetters:
How valid would it be to send an entire board, 16X19x0.094 inches, through the wave solder process x number of times, 1x, 2x, 3x, etc., and call it thermal stress. Also the extracted coupon size are ¾ x 1/2 inches removed with a router . What are the Pros and Cons with this method of thermal stress in accordance with IPC guidelines.
"X"
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