I will say IPC TM-650, Method 2.6.27. Not knowing what you meant by the
term shock, this TM simulates the stress of thermal excursions
experienced by the printed board during reflow processing.
Dewey

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Victor Hernandez
Sent: Tuesday, February 01, 2011 12:21 PM
To: [log in to unmask]
Subject: [TN] IPC-TM-650 2.6.8, Thermal Stress, PTHs

Folks,

   As I understand the above mentioned Test Method is reserve for PTH
product/boards.   What application is used when all of the PTH are
filled with non conductive maters, plated over, planarized and covered
with solder mask.   I don't see how the above test would shock the IP
layers.

"X"


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