Sorry,
had a typo—should be IPC-TR-486.
Werner
-----Original Message-----
From: [log in to unmask]
To: [log in to unmask]
Cc: [log in to unmask]
Sent: Thu, Feb 3, 2011 10:06 am
Subject: RE: [TN] IPC-TM-650 2.6.8, & 2.6.27, Thermal Stress, PTHs & thick boards
Werner,
I was not able to find in a search the IPC-TR-487 document you stated. IPC Online Catalogue.
Victor,
From: Werner Engelmaier [mailto:[log in to unmask]]
Sent: Wednesday, February 02, 2011 8:43 PM
To: Hernandez, Victor G; [log in to unmask]
Subject: Re: [TN] IPC-TM-650 2.6.8, Thermal Stress, PTHs
Hi Victor,
These TMs have all been updated—and even 'back when,' there were lots of PTHs without pins in them—those were the ones we worried about.
The technologies may have changed and dimensions may have shrunk, but the basic damage mechanisms are still at work—and the TMs have changed as well [you should get and read IPC-TR-487] to accommodate needed more subtle and refined approaches [TM-650, 2.6.26 & 2.6.27].
We now have failure modes not seen previously—still, the underlying damage mechanism is differential thermal expansion and contraction.
Werner
-----Original Message-----
From: [log in to unmask]
To: [log in to unmask]
Cc: [log in to unmask]
Sent: Wed, Feb 2, 2011 4:28 pm
Subject: RE: [TN] IPC-TM-650 2.6.8, Thermal Stress, PTHs
Werner,
Enlightened me.
Beside IPC-TM-650 section 2.6.8 , is there a good explanation of the intent of the test and does it address technology of the product. Back when many of the IPC TM were written the common product was Pin In Hole components. Now the technology has changed a lot, buried vias, micro vias, filled via, etc, yet we use some of those old TM.
Victor,
From: Werner Engelmaier [mailto:[log in to unmask]]
Sent: Tuesday, February 01, 2011 7:10 PM
To: Hernandez, Victor G
Subject: Re: [TN] IPC-TM-650 2.6.8, Thermal Stress, PTHs
No,
While the heating is rapid, "shocking" is not an issue.
Werner
-----Original Message-----
From: [log in to unmask]
To: [log in to unmask]
Cc: [log in to unmask]
Sent: Tue, Feb 1, 2011 4:13 pm
Subject: RE: [TN] IPC-TM-650 2.6.8, Thermal Stress, PTHs
Werner,
Isn’t part of the float test to shock the inner layer post, IP, as the molten solder travels up the PTH wall to the other side of the board searching for weak links.
“X”,
From: Werner Engelmaier [mailto:[log in to unmask]]
Sent: Tuesday, February 01, 2011 1:44 PM
To: [log in to unmask]; Hernandez, Victor G
Subject: Re: [TN] IPC-TM-650 2.6.8, Thermal Stress, PTHs
Hi Victor "X" (?),
Why would you want to "shock the IP layers"? What would that accomplish?
What you want to do, and this test does, is expose your PCB to elevated temperatures to get an idea as how it is holding up in temperature excursions during soldering operations and subsequent operational T-cycles.
Werner
-----Original Message-----
From: Victor Hernandez <[log in to unmask]>
To: [log in to unmask]
Sent: Tue, Feb 1, 2011 2:20 pm
Subject: [TN] IPC-TM-650 2.6.8, Thermal Stress, PTHs
Folks,
As I understand the above mentioned Test Method is reserve for PTH
product/boards. What application is used when all of the PTH are filled with
non conductive maters, plated over, planarized and covered with solder mask. I
don't see how the above test would shock the IP layers.
"X"
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