By the way, been discussing LTCC vias with the Eagle. Gold system, vias
mixed system (Au/Ag). Substrates 2x2", Kovar frame, Molly sink. Some vias
not entirely filled, look more like barrels than plugs. Squeege printing
issue. Did not like the vias, but was overrun by QC/QA/PM. So the
substrates go for production the next days. The Eagle believes they might
work.
Q: LTCC structure very stiff and little dx/X/dy/Y, but what about dz/Z?
Assume that the poorly filled vias got a rudimentary contact with the
imbedded power trace or GND, do you think there is any dt/T -55/+125 risk?
Inge
On 2 February 2011 21:36, Werner Engelmaier <[log in to unmask]> wrote:
> Hi Inge,
> Those were 'the good old days'—well. very good in terms of resources and
> freedom, not so good when it came to the organization [I still have an
> occasional nightmare].
> This equation has been somewhat updated since, it is in IPC-D-279 and I
> teach it in some of my workshops.
> You sure have an incredible memory and/or a incredibly organized reference
> library.
> Werner
>
>
>
>
>
> -----Original Message-----
> From: Inge Hernefjord <[log in to unmask]>
> To: TechNet E-Mail Forum <[log in to unmask]>; Werner Engelmaier <
> [log in to unmask]>
> Sent: Wed, Feb 2, 2011 3:21 pm
> Subject: Re: [TN] IPC-TM-650 2.6.8, Thermal Stress, PTHs
>
>
> W, I have a old report, *Predicting Plated-Through-Hole Reliability in a
> High Temperature Manufacturing Environment, *in which one equattion is '
> Engelmaier eq.'
> The report is written by DEC . If it could be of any help, I can send a
> copy, alt. you may find it in IEEE'S ARCHIVE.
>
>
>
> Inge
>
>
>
> On 1 February 2011 20:44, Werner Engelmaier <[log in to unmask]> wrote:
>
>> Hi Victor "X" (?),
>>
>> Why would you want to "shock the IP layers"? What would that accomplish?
>> What you want to do, and this test does, is expose your PCB to elevated
>> temperatures to get an idea as how it is holding up in temperature
>> excursions during soldering operations and subsequent operational T-cycles.
>> Werner
>>
>>
>>
>>
>>
>>
>> -----Original Message-----
>> From: Victor Hernandez <[log in to unmask]>
>> To: [log in to unmask]
>> Sent: Tue, Feb 1, 2011 2:20 pm
>> Subject: [TN] IPC-TM-650 2.6.8, Thermal Stress, PTHs
>>
>>
>> Folks,
>>
>>
>>
>> As I understand the above mentioned Test Method is reserve for PTH
>>
>> product/boards. What application is used when all of the PTH are filled
>> with
>>
>> non conductive maters, plated over, planarized and covered with solder
>> mask. I
>>
>> don't see how the above test would shock the IP layers.
>>
>>
>>
>> "X"
>>
>>
>>
>>
>>
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