W, I have a old report, *Predicting Plated-Through-Hole Reliability in a
High Temperature Manufacturing Environment, *in which one equattion is '
Engelmaier eq.'
The report is written by DEC . If it could be of any help, I can send a
copy, alt. you may find it in IEEE'S ARCHIVE.



Inge



On 1 February 2011 20:44, Werner Engelmaier <[log in to unmask]> wrote:

>  Hi Victor "X" (?),
>
>  Why would you want to "shock the IP layers"? What would that accomplish?
> What you want to do, and this test does, is expose your PCB to elevated
> temperatures to get an idea as how it is holding up in temperature
> excursions during soldering operations and subsequent operational T-cycles.
> Werner
>
>
>
>
>
>
> -----Original Message-----
> From: Victor Hernandez <[log in to unmask]>
> To: [log in to unmask]
> Sent: Tue, Feb 1, 2011 2:20 pm
> Subject: [TN] IPC-TM-650   2.6.8,  Thermal Stress,  PTHs
>
>
>  Folks,
>
>
>
>   As I understand the above mentioned Test Method is reserve for PTH
>
> product/boards.   What application is used when all of the PTH are filled
> with
>
> non conductive maters, plated over, planarized and covered with solder
> mask.   I
>
> don't see how the above test would shock the IP layers.
>
>
>
> "X"
>
>
>
>
>
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