I agree with that. That is called dispositioning of non-compliant PWBs.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Gary Ferrari
Sent: Thursday, February 17, 2011 10:50 AM
To: [log in to unmask]
Subject: Re: [TN] Electrical Clearance as stated in IPC standards
I fully agree with Jack and maybe wasn't totally clear. If boards have
not passed inspection, but are desperately needed, the customer may ask
to review the nature of the rejects and exercise an option to override
the rejection and accept the rejected boards to meet immediate needs.
Gary
On 2/17/2011 10:51 AM, Jack Olson wrote:
> I agree with what Gary says in principle. Clearances set by voltage
> requirements will be much larger than MINIMUM clearances for different classes
> in IPC.
> But I have to comment that since the scenario put forth by Wee Mei stated
> "during bare board inspection (class 3 requirement)", if the defects are
> rejectable by criteria in IPC-A-600, then the boards are rejectable. period.
> What I mean is, an inspector can't be expected to know what the circuit is
> intended to do, and if manufacturing defects violate the criteria, its rejectable.
> If someone else wants to evaluate the situation and determines that the
> defect won't affect the circuit performance, then the boards MAY be accepted
> anyway.
> Your quote said "the argument kick-in that it is not a violation and can be
> acceptable" is half right. It CAN be acceptable, but it IS a violation.
> I hope the manufacturer is not bullying you into accepting defective boards
> based on knowledge of the circuit, telling you not to worry about the defect
> because the circuit should still work okay. It should be the customer that
> makes that decision, right?
>
> Jack
>
> .
>
> On Thu, 17 Feb 2011 10:14:10 -0500, Gary Ferrari
> <[log in to unmask]> wrote:
>
>> Lum Wee Mei,
>>
>> Minimum electrical clearance is based on the voltage used in the design.
>> The greater the voltage, the greater the required spacing. In your
>> example, the spacing used was much larger than the required minimum
>> electrical clearance, based on voltage. Although the defect reduced the
>> spacing beyond what is considered acceptable, per the artwork, the end
>> result still did not violate the voltage based electrical clearance. In
>> this case, the board may be accepted, this time. The supplier should not
>> count on you accepting such product quality in the future.
>>
>> Regards,
>>
>> Gary F.
>>
>> On 2/17/2011 12:26 AM, Lum Wee Mei wrote:
>>> Dear All,
>>>
>>> Until now, I am still very curious about this term "electrical clearance" that
> is used on the IPC standards. Very often, the standard will says something like
> "it is acceptable as long as it meets the electrical clearance". As I did not have
> the IPC standards with me when I right this, allow me to use a scenario to
> illustrate my query :
>>>
>>> A digital PCB has some pockets of power and ground area fills with minimum
> trace width/clearance of say 6mil/6mil (0.15mm/0.15mm) and power trace
> width of 50mil. During bare board inspection (Class 3 requirement), one of the
> power trace that run along side of the ground fill, has an excessive copper
> protrusion that reduce the physical conductor to conductor clearance by 60%.
> Based on the IPC-A-600, it has violate the conductor to conductor clearance.
> However, the argument kick-in that it is not a violation and can be acceptable
> because the remaining clearance of 40% is much larger than the electrical
> clearance stated in IPC-2221 for that application. Now, how should this be
> resolved?
>>>
>>> Thanks and Regards,
>>> ~ Wee Mei ~
>>>
>
>
>
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