Lum Wee Mei,
Minimum electrical clearance is based on the voltage used in the design.
The greater the voltage, the greater the required spacing. In your
example, the spacing used was much larger than the required minimum
electrical clearance, based on voltage. Although the defect reduced the
spacing beyond what is considered acceptable, per the artwork, the end
result still did not violate the voltage based electrical clearance. In
this case, the board may be accepted, this time. The supplier should not
count on you accepting such product quality in the future.
Regards,
Gary F.
On 2/17/2011 12:26 AM, Lum Wee Mei wrote:
> Dear All,
>
> Until now, I am still very curious about this term "electrical clearance" that is used on the IPC standards. Very often, the standard will says something like "it is acceptable as long as it meets the electrical clearance". As I did not have the IPC standards with me when I right this, allow me to use a scenario to illustrate my query :
>
> A digital PCB has some pockets of power and ground area fills with minimum trace width/clearance of say 6mil/6mil (0.15mm/0.15mm) and power trace width of 50mil. During bare board inspection (Class 3 requirement), one of the power trace that run along side of the ground fill, has an excessive copper protrusion that reduce the physical conductor to conductor clearance by 60%. Based on the IPC-A-600, it has violate the conductor to conductor clearance. However, the argument kick-in that it is not a violation and can be acceptable because the remaining clearance of 40% is much larger than the electrical clearance stated in IPC-2221 for that application. Now, how should this be resolved?
>
> Thanks and Regards,
> ~ Wee Mei ~
>
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