Hi

That is a misinterpretation, minimum clearance stated in the PCB spec is 
usually the minimum gap used in the design, not the absolute minimum 
isolation distance.
The minimum clearance for a specific area on the board is still related to 
the artwork for the same area.

Cheers
Grunde






Lum Wee Mei <[log in to unmask]> 
Sent by: TechNet <[log in to unmask]>
17.02.2011 06:28
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[TN] Electrical Clearance as stated in IPC standards






Dear All,
 
Until now, I am still very curious about this term "electrical clearance" 
that is used on the IPC standards. Very often, the standard will says 
something like "it is acceptable as long as it meets the electrical 
clearance". As I did not have the IPC standards with me when I right this, 
allow me to use a scenario to illustrate my query :
 
A digital PCB has some pockets of power and ground area fills with minimum 
trace width/clearance of say 6mil/6mil (0.15mm/0.15mm) and power trace 
width of 50mil. During bare board inspection (Class 3 requirement), one of 
the power trace that run along side of the ground fill, has an excessive 
copper protrusion that reduce the physical conductor to conductor 
clearance by 60%. Based on the IPC-A-600, it has violate the conductor to 
conductor clearance. However, the argument kick-in that it is not a 
violation and can be acceptable because the remaining clearance of 40% is 
much larger than the electrical clearance stated in IPC-2221 for that 
application. Now, how should this be resolved?
 
Thanks and Regards,
~ Wee Mei ~

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