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January 2011

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From:
"Thayer, Wayne - IIW" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Thayer, Wayne - IIW
Date:
Tue, 25 Jan 2011 10:34:24 -0500
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Hi Lars-

We can always count on Joyce for the succinct answers!  No wasted words!

Almost always, a quick test is done at the wafer level and a map is created showing where the bad parts are.  But the quick test is not complete--on Xilinx parts (and probably most FPGA's), most of the I/O remains unchecked.  The whole testing process is done based on cost optimization--most defects are best caught at the wafer level (prior to investing in packaging), so they check for the most likely failures there.  But it becomes expensive to get speed/voltage ratings at that level, so they wait until the unit is packaged to get those.

Wayne

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Joyce Koo
Sent: Tuesday, January 25, 2011 8:31 AM
To: [log in to unmask]
Subject: Re: [TN] TEST OF BARE DIE CIRCUITS

Both.
--------------------------
Sent using BlackBerry


----- Original Message -----
From: Lars Wallin [mailto:[log in to unmask]]
Sent: Tuesday, January 25, 2011 08:22 AM
To: [log in to unmask] <[log in to unmask]>
Subject: [TN] TEST OF BARE DIE CIRCUITS

Hello Technet,

Can anyone short describe which sort of test methods are used for testing bare die circuits? Are they tested on the Waffer level or after cutting.

Best Regards
Lars Wallin
IPC European Representative
Location: Stockholm, Sweden
Phone:  +46 8 26 10 07
Mobile: +46 70 212 74 39
Email: [log in to unmask]<mailto:[log in to unmask]>

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