Steve,
What me joking about the EU—anybody who can mindlessly ban Pb from solder, certainly can regulate banana curvature—I am hearing the size of snowflakes is next [now that is a joke]
Werner
-----Original Message-----
From: Steve Gregory <[log in to unmask]>
To: 'TechNet E-Mail Forum' <[log in to unmask]>; 'Werner Engelmaier' <[log in to unmask]>
Sent: Wed, Dec 15, 2010 9:43 am
Subject: RE: NTC [TN] X-ray inspection of voids under chip caps and resistors
Werner, I thought you were just making a joke about "the EU specifying the
allowable curvature of bananas", but you weren't!
http://tinyurl.com/y9t8lr3
Geeze...don't know what to say. Can't believe that there's actually a
quality standard written for bananas
Steve
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Werner Engelmaier
Sent: Wednesday, December 15, 2010 8:24 AM
To: [log in to unmask]
Subject: Re: [TN] X-ray inspection of voids under chip caps and resistors
Hi Phil,
It is an old story---just because you can measure something---even with, or
maybe because of very expensive equipment, does not make it necessarily
significant or important. It has been shown over and over again, that voids
in the normally produced ranges have no negative [there is actually a slight
positive effect under some limited special conditions] reliability impact.
It is like the EU specifying the allowable curvature of bananas.
Werner
-----Original Message-----
From: David D. Hillman <[log in to unmask]>
To: [log in to unmask]
Sent: Wed, Dec 15, 2010 8:11 am
Subject: Re: [TN] X-ray inspection of voids under chip caps and resistors
Hi Phil - There are a number of X-ray systems on the market that can
accomplish the task per the NASA Workmanship standards but the question
really should be "why is there such a requirement?". Rockwell Collins,
RIM, Indium and Dage are finishing up a BGA voiding study that shows voids
are not a "primary" issue to solder joint integrity. We will be proposing
to the JSTD-001 committee new BGA voiding requirements, in collaboration
with a number of other industry investigators, at the IPC 2011 Fall
meeting. I find it a bit hard to believe that a chip resistor needs a
stricter solder joint void requirement than a BGA component.
Dave Hillman
Rockwell Collins
[log in to unmask]
Phil Bavaro <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
12/14/2010 06:06 PM
Please respond to
TechNet E-Mail Forum <[log in to unmask]>; Please respond to
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To
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Subject
[TN] Xray inspection of voids under chip caps and resistors
Are any Technetters working with the newly drafted Workmanship standard
(WSF 11122010) from NASA?
I am surprised that they are intending to implement xray inspection of
voiding on chip caps and resistors.
It appears they want us to determine the percentage of voids greater
than 1 mil and then add up the areas both for the beneath component and
then the external fillets.
While I suppose it is progress to have NASA embracing water soluble
fluxes, this seems like a huge hurdle to have to cross first.
Here is the requirement as drafted:
1. The X-ray process (including equipment, operator and procedure)
shall be capable of discerning a solder void that is one thousandth of
an inch (0.001") in diameter. If the supplier's X-ray capability is not
adequate, specimens can be sent to GSFC for X-ray.
2. For each PWA or coupon examined via X-ray, five worst case
examples on the PWA or coupon shall be selected for measurement to show
compliance with the following criteria:
a. For parts with chip package styles (e.g. resistors, diodes,
capacitors) and for flatpacks, a minimum of 75% of the solderable area
directly under the end cap or lap portion of the lead shall be
filled/wetted (i.e., using the solderable area under the end cap or lead
as the denominator and that area less all absences of solder - voids,
areas where the solder did not wet, overhangs due to misregistration,
etc. - as the numerator). This requirement applies only to the area
directly underneath the end cap (chip packages) and lap portion of the
lead (flatpacks), and does not apply to other package styles and does
not include any portion of the fillet.
b. For all package styles, the void area in the fillet area shall
include only those areas that are completely enclosed with solder, and
shall not exceed 10% of the area covered by the fillet.
I know that some xray systems have pretty helpful software packages for
void detection, but I don't remember any that looked at solder
percentages beneath the component versus fillet versus both.
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