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From:
"David D. Hillman" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, [log in to unmask]
Date:
Wed, 15 Dec 2010 07:11:15 -0600
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Hi Phil - There are a number of X-ray systems on the market that can 
accomplish the task per the NASA Workmanship standards but the question 
really should be "why is there such a requirement?". Rockwell Collins, 
RIM, Indium and Dage are finishing up a BGA voiding study that shows voids 
are not a "primary" issue to solder joint integrity. We will be proposing 
to the JSTD-001 committee new BGA voiding requirements, in collaboration 
with a number of other industry investigators, at the IPC 2011 Fall 
meeting. I find it a bit hard to believe that a chip resistor needs a 
stricter solder joint void requirement than a BGA component.

Dave Hillman
Rockwell Collins
[log in to unmask]



Phil Bavaro <[log in to unmask]> 
Sent by: TechNet <[log in to unmask]>
12/14/2010 06:06 PM
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TechNet E-Mail Forum <[log in to unmask]>; Please respond to
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Subject
[TN] Xray inspection of voids under chip caps and resistors






Are any Technetters working with the newly drafted Workmanship standard
(WSF 11122010) from NASA?

I am surprised that they are intending to implement xray inspection of
voiding on chip caps and resistors.

It appears they want us to determine the percentage of voids greater
than 1 mil and then add up the areas both for the beneath component and
then the external fillets.

While I suppose it is progress to have NASA embracing water soluble
fluxes, this seems like a huge hurdle to have to cross first.

 

Here is the requirement as drafted:

 

1.       The X-ray process (including equipment, operator and procedure)
shall be capable of discerning a solder void that is one thousandth of
an inch (0.001") in diameter.  If the supplier's X-ray capability is not
adequate, specimens can be sent to GSFC for X-ray. 

2.       For each PWA or coupon examined via X-ray, five worst case
examples on the PWA or coupon shall be selected for measurement to show
compliance with the following criteria: 

a.       For parts with chip package styles (e.g. resistors, diodes,
capacitors) and for flatpacks, a minimum of 75% of the solderable area
directly under the end cap or lap portion of the lead shall be
filled/wetted (i.e., using the solderable area under the end cap or lead
as the denominator and that area less all absences of solder - voids,
areas where the solder did not wet, overhangs due to misregistration,
etc. - as the numerator).   This requirement applies only to the area
directly underneath the end cap (chip packages) and lap portion of the
lead (flatpacks), and does not apply to other package styles and does
not include any portion of the fillet. 

b.       For all package styles, the void area in the fillet area shall
include only those areas that are completely enclosed with solder, and
shall not exceed 10% of the area covered by the fillet. 

 

I know that some xray systems have pretty helpful software packages for
void detection, but I don't remember any that looked at solder
percentages beneath the component versus fillet versus both.

 

 


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