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October 2010

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Subject:
From:
"Glidden, Kevin" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Glidden, Kevin
Date:
Mon, 4 Oct 2010 08:44:53 -0400
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Wee,

If you have not already, you might also reference IPC-A-600 and IPC-6012 which give great photos and illustrations of the internally observable conditions related to PCB fabrication.

-----Original Message-----
From: Paul Reid [mailto:[log in to unmask]] 
Sent: Friday, October 01, 2010 11:40 AM
To: [log in to unmask]
Subject: Re: [TN] Microsection

Hi Wee,

Microsections (XS) do take awhile to learn how to read and Ian is very
accomplished at XS interpretation.

From a quality point of view you can review copper thicknesses, line
width, hole roughness, drill smear, nail heading, etch back and the list
goes on, and on. You get a good insight on many process steps used to
fabricate PWBs, but that comes with experience.

The industry processes microsections on any number of planes, through
any number of structures, to find out different things about the board.
A vertical section through the via is most common. Horizontal sections
help understand registrations and on occasion find CAF (Ian did once). 

My area of expertise is in understanding the reliability implications of
failed vias. You may find my column Reid on Reliability in iconnect007
useful. Here is a link to a column on PTH wear out.
http://www.pcb007.com/pages/zone.cgi?a=58530&artpg=1&topic=0

The column will link to other columns that address interpretation of
failed coupons by means of microsections.

Sincerely, 
Paul Reid 

Program Coordinator 
PWB Interconnect Solutions Inc. 
235 Stafford Rd., West, Unit 103 
Nepean, Ontario 
Canada, K2H 9C1 
613 596 4244 ext. 229 
Skype paul_reid_pwb 
[log in to unmask] <mailto:[log in to unmask]> 


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Ian Hanna
Sent: October 1, 2010 10:41 AM
To: [log in to unmask]
Subject: Re: [TN] Microsection

Wee Mei -- Vias typically represent worst-case drilling and plating and 
are a good indication of the overall board build quality...I would think

they were doing you a favour.  In my former life as quality in a fab
house 
I would examine vias for my internal purposes, but forward the larger
PTH 
as part of the microsection puck unless otherwise specified by my 
customers -- Cheers -- Ian





Lum Wee Mei <[log in to unmask]> 
Sent by: TechNet <[log in to unmask]>
10/01/2010 10:35 AM
Please respond to
TechNet E-Mail Forum <[log in to unmask]>; Please respond to
Lum Wee Mei <[log in to unmask]>


To
[log in to unmask]
cc

Subject
[TN] Microsection






With regard to PCB microsection, is it a must that microsection has to
be 
done on plated through holes. I received a pre- and post microsection 
samples from my vendor and noticed that they are done across the plated 
through via. Of course, the solder cannot flow through the walls of the 
vias on the post solder sample. Can I accept this post solder sample and

use it to verify the fabrication process? If yes, what are the reasons.
 
I am learning the trade by myself and would appreciate I can learn from 
the experts in the field. If there is any articles on how to interpret
the 
microsection sample for PCB such how to differentiate electroless copper

from copper plating and then the tin-lead plating in the wall or pad 
surface, etc would also be most appreciated.
 
Thanks and Regards,
~ Wee Mei ~

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