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Subject:
From:
Ioan Tempea <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Ioan Tempea <[log in to unmask]>
Date:
Tue, 7 Sep 2010 09:23:20 -0400
Content-Type:
text/plain
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text/plain (1 lines)
Eric,

Even the stainless squeegees will scoop paste on large surfaces. This is why window pane openings have been implemented, to divide big areas. Besides that, not enough squeegee pressure, too high speeds, negative snap off are only a few causes of thinner paste deposits.

Good luck,

Ioan Tempea, ing.
Ingénieur Principal de Fabrication / Senior Manufacturing Engineer
T | 450.967.7100 ext.244
E | [log in to unmask] 
W | www.digico.cc

N’imprimer que si nécessaire – Print only if you must

-----Message d'origine-----
De : Eric Christison [mailto:[log in to unmask]] 
Envoyé : September-07-10 9:13 AM
À : [log in to unmask]
Objet : Re: [TN] Stencil thickness v solder paste height

Thanks Guy,

I understand now.

So if I start from easiest case, a perfectly flat board, then the 
thickness of the paste is equal to the thickness of the stencil?

Any imperfection on the board will make the paste thicker, it can never 
make it thinner?

Other complications such as improper printer settings could reduce the 
paste volume and thus result in the paste thickness in some areas being 
thinner than the stencil?

Regards,



On 07/09/2010 13:56, Guy Ramsey wrote:
> I believe Bob was referring you to the way solder mask can act as a shim. It
> lifts the stencil off the copper effectively creating a non-contact solder
> print. Solder mask thickness can vary depending on the features being
> masked. Tented vias can be covered with a blob of mask. This might shim your
> stencil off the board more at that location, causing print variation.
> There are DFM concerns. Silk screen on the board surface can do the same
> thing.
> If not given proper consideration these conditions and easily double the
> thickness of the print.
>
> If the stencil is not properly designed or created for the application, it
> is possible for print volume to be less than optimal, leaving poorly formed
> solder deposits on the board. The same can be caused by bad paste, improper
> printer settings, malfunctioning printers, very humid environments . . . use
> a fishbone diagram to explore the possibilities, manpower, materials,
> methods, machines, environment. How might they interact to produce variation
> in solder paste deposits?
>
> Guy
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Eric Christison
> Sent: Tuesday, September 07, 2010 4:24 AM
> To: [log in to unmask]
> Subject: Re: [TN] Stencil thickness v solder paste height
>
> Thanks Bob,
>
> A quick look tells me that solder paste volume can vary by +/-50% which
> seems a lot. Is it reasonable to assume that the blob height will never
> be more than the height of the stencil or can the edges be pulled
> upwards when the stencil is lifted?
>
> Regards,
>
>
>
> On 06/09/2010 19:20, Robert Kondner wrote:
>    
>> Eric,
>>
>>    Good question, if you look at the web sites for folks that vend 3D paste
>> inspection system I bet you can find some good data.
>>
>>    What I have seen is the surface of the PCB is not flat, solder mask and
>> silk screen ink act like hold offs at time. Tented vias for big high
>>      
> blobs.
>    
>>    And, of course, there is scoping of paste from plastic squeegees.
>>
>> Bob Kondner
>>
>> -----Original Message-----
>> From: TechNet [mailto:[log in to unmask]] On Behalf Of Eric Christison
>> Sent: Monday, September 06, 2010 11:02 AM
>> To: [log in to unmask]
>> Subject: [TN] Stencil thickness v solder paste height
>>
>> I guess this is an easy one for most you...
>>
>> If solder paste is applied to a PWB with a 0.10+/-0.01mm thick stencil
>> what is the minimum height of paste I can expect to get on the PWB?
>>
>> Sn95.5Ag3.8Cu0.7 paste , DAP (20 - 38 μm) or Sn95.5Ag4.0Cu0.5, IPC type
>> 3 (25-45 μm) if composition makes much difference.
>>
>> Thanks,
>>
>>
>>      
>    

-- 
Eric Christison
Consumer&  Micro group
Imaging Division

STMicroelectronics (R&D) Ltd
33 Pinkhill
Edinburgh EH12 7BF
United Kingdom

Tel:	+44 (0)131 336 6165
Fax:	+ 44 (0)131 336 6001




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