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September 2010

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Subject:
From:
Joe Venditti <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Joe Venditti <[log in to unmask]>
Date:
Fri, 24 Sep 2010 18:08:46 -0400
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Mumtaz Bora <[log in to unmask]> wrote:

>Thank-you Tim. 
>
>
>Mumtaz Bora
>
>Senior Packaging Engineer
>
>Peregrine Semiconductor
>
>9380 Carroll Park Drive
>
>San Diego, CA 92121
>
>858-795-0112-direct
>
>858-731-9499 -fax
>
>[log in to unmask]
>
> 
>
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Whittaker, Dewey (EHCOE)
>Sent: Monday, September 13, 2010 10:21 AM
>To: [log in to unmask]
>Subject: Re: [TN] FW: IPC-TM-650, 2.6.8, BAKING OF PWB QUESTION,
>
>Which is worse: knowing; or not knowing?
>IPC-TM-650, Method 2.6.8 - not knowing
>IPC-TM-650, Method 2.6.27 - knowing
>Dewey
>
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Victor Hernandez
>Sent: Monday, September 13, 2010 10:02 AM
>To: [log in to unmask]
>Subject: [TN] FW: IPC-TM-650, 2.6.8, BAKING OF PWB QUESTION,
>
>Fellow TechNetters:
>
>   Which is worse:   The initial shock of the molten solder or the Constance thermal cycling?   On thicker boards, 220 mils, when the solder did not wick the entire barrel.  Is this a valid thermal shock?
>
>"X"
>
>-----Original Message-----
>From: Hernandez, Victor G
>Sent: Wednesday, August 18, 2010 9:22 AM
>To: TechNet E-Mail Forum
>Cc: Hernandez, Victor G
>Subject: IPC-TM-650, 2.6.8, BAKING OF PWB QUESTION, 
>
>Fellow TechNetters:
>
>   IPC-TM-650   2.6.8
>
>Can this test method be used for LF application:
>Sample is 24 layers mid plane, FR4, back/front side drilling,
>0.019 & 0.020 finish hole size,
>
>Any comments will greatly be appreciated.
>
>Victor ( "X" )
>
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Paul Reid
>Sent: Tuesday, July 13, 2010 3:55 PM
>To: [log in to unmask]
>Subject: Re: [TN] BAKING OF PWB QUESTION
>
>My rule of thumb has been 105°C for 4 hours max.
>
>Consider
>- Time and temperature degrades the dielectric.
>- Time and temperature degrades the surface finish.
>- Lead/free applications have a greater need for baking as compared to tin/lead applications.
>
>
>Paul Reid 
>
>Program Coordinator 
>PWB Interconnect Solutions Inc. 
>235 Stafford Rd., West, Unit 103 
>Nepean, Ontario 
>Canada, K2H 9C1 
>613 596 4244 ext. 229 
>Skype paul_reid_pwb 
>[log in to unmask] <mailto:[log in to unmask]> 
>
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Roberts, Jon (SA-1)
>Sent: July 13, 2010 11:35 AM
>To: [log in to unmask]
>Subject: [TN] BAKING OF PWB QUESTION
>
>Is there a rule of thumb or any best manufacturing practices of how long
>after baking does the PWB have to be processed?   Jon
>
>
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