Hi Victor,
Just guessing, I would take the float time for 62-mil PCBs, divide by 62 and multiply by 220, and make that my float time.
Werner
-----Original Message-----
From: [log in to unmask]
To: [log in to unmask]
Cc: [log in to unmask]
Sent: Tue, Sep 14, 2010 10:03 am
Subject: RE: [TN] FW: IPC-TM-650, 2.6.8
Thank you for sharing your expertise. This was my initialconcern when I was asked to conduct Thermal Stress on thicker boards, 220 mils,which did not meet our previous TM 650 design parameters guidelines,thickness. I did see that the majority of the PTHs did not fill completely,100%, with solder as the 62 thousand boards did. Also notice that non wet ofthe annular rings. Perhaps due to the fluxing soak time which is not specifiedin any article/document. On a 1x shock, only one side would see the actualtemperature of the molten solder while on the 2x I could flip the sample aroundto shock it on both sides.
If you were a guessing man, what would you suggest thefloat time on 220 mils thickness boards be? Any idea how I could establishthat dwell time on scrap samples without inducing excessive damage to thesamples.
“X”
From: Werner Engelmaier[mailto:[log in to unmask]]
Sent: Tuesday, September 14, 2010 8:32 AM
To: [log in to unmask]; Hernandez, Victor G
Subject: Re: [TN] FW: IPC-TM-650, 2.6.8
Hi Victor,
Dewey pointed you in the right direction—use IPC-TM-650, Method 2.6.27 for yourtest.
IPC-TM-650, 2.6.8 was never intended for thicker PWBs, even though they need a test like this even more, that was the reason for 2.6.27.
If you do not get the holes to fill, that means that the PWB never reached uniform temperature, thus the test is invalid for its purpose—it needs a longer time floating.
Werner
-----Original Message-----
From: Victor Hernandez <[log in to unmask]>
To: [log in to unmask]
Sent: Tue, Sep 14, 2010 8:07 am
Subject: Re: [TN] FW: IPC-TM-650, 2.6.8
Folks,
What is the industry doing with Thermal Stress testing for boards thicker than
the traditionally 62 thousand. To me this is like LF, it was introduce, so
find solution to overcome unforeseeable issues. The larger/thicker board are
here so what is the acceptable method of testing under TM-650.
"X"
From: Whittaker, Dewey (EHCOE) [mailto:[log in to unmask]]
Sent: Monday, September 13, 2010 12:55 PM
To: Hernandez, Victor G
Subject: RE: [TN] FW: IPC-TM-650, 2.6.8, BAKING OF PWB QUESTION,
Re-read my first sentence. There are too many variables. All the initial
requirements for hole fill were based on 0.063 thick printed boards.
Dewey
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Monday, September 13, 2010 10:44 AM
To: Whittaker, Dewey (EHCOE)
Cc: [log in to unmask]
Subject: RE: [TN] FW: IPC-TM-650, 2.6.8, BAKING OF PWB QUESTION,
On thicker boards, is it expected to fill the PTH with solder during a Thermal
Stress/Float Test? Aspect ratio plays a part. What is expected.
"X"
-----Original Message-----
From: Whittaker, Dewey (EHCOE) [mailto:[log in to unmask]]
Sent: Monday, September 13, 2010 12:38 PM
To: Hernandez, Victor G
Subject: RE: [TN] FW: IPC-TM-650, 2.6.8, BAKING OF PWB QUESTION,
This is a design/processing issue. I thought you wanted to know which one was an
acceptable test for use in LF applications.
Dewey
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Monday, September 13, 2010 10:32 AM
To: Whittaker, Dewey (EHCOE)
Cc: [log in to unmask]
Subject: RE: [TN] FW: IPC-TM-650, 2.6.8, BAKING OF PWB QUESTION,
I want to known in either case but need to understand why things happened. In
62 thousands boards one can see that the PTH filled with solder, therefore heat
was disperse through the layer thickness and IPs. On thicker boards, 220
mils, the PTH holes did not fill with solder. Thus the question, did the heat
from the molten solder travel the length of the barrel and IPs.
"X"
-----Original Message-----
From: Whittaker, Dewey (EHCOE) [mailto:[log in to unmask]]
Sent: Monday, September 13, 2010 12:21 PM
To: TechNet E-Mail Forum; Hernandez, Victor G
Subject: RE: [TN] FW: IPC-TM-650, 2.6.8, BAKING OF PWB QUESTION,
Which is worse: knowing; or not knowing?
IPC-TM-650, Method 2.6.8 - not knowing
IPC-TM-650, Method 2.6.27 - knowing
Dewey
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Victor Hernandez
Sent: Monday, September 13, 2010 10:02 AM
To: [log in to unmask]
Subject: [TN] FW: IPC-TM-650, 2.6.8, BAKING OF PWB QUESTION,
Fellow TechNetters:
Which is worse: The initial shock of the molten solder or the Constance
thermal cycling? On thicker boards, 220 mils, when the solder did not wick the
entire barrel. Is this a valid thermal shock?
"X"
-----Original Message-----
From: Hernandez, Victor G
Sent: Wednesday, August 18, 2010 9:22 AM
To: TechNet E-Mail Forum
Cc: Hernandez, Victor G
Subject: IPC-TM-650, 2.6.8, BAKING OF PWB QUESTION,
Fellow TechNetters:
IPC-TM-650 2.6.8
Can this test method be used for LF application:
Sample is 24 layers mid plane, FR4, back/front side drilling,
0.019 & 0.020 finish hole size,
Any comments will greatly be appreciated.
Victor ( "X" )
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Paul Reid
Sent: Tuesday, July 13, 2010 3:55 PM
To: [log in to unmask]
Subject: Re: [TN] BAKING OF PWB QUESTION
My rule of thumb has been 105°C for 4 hours max.
Consider
- Time and temperature degrades the dielectric.
- Time and temperature degrades the surface finish.
- Lead/free applications have a greater need for baking as compared to tin/lead
applications.
Paul Reid
Program Coordinator
PWB Interconnect Solutions Inc.
235 Stafford Rd., West, Unit 103
Nepean, Ontario
Canada, K2H 9C1
613 596 4244 ext. 229
Skype paul_reid_pwb
[log in to unmask] <mailto:[log in to unmask]>
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Roberts, Jon (SA-1)
Sent: July 13, 2010 11:35 AM
To: [log in to unmask]
Subject: [TN] BAKING OF PWB QUESTION
Is there a rule of thumb or any best manufacturing practices of how long
after baking does the PWB have to be processed? Jon
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