********* This has been discussed on the forum before. 

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of prashant chopra
Sent: 21 June 2010 12:27
To: [log in to unmask]
Subject: [TN] Use of vias as ICT pads

Hi,
 
Need input regarding the use of vias for probing during the ICT process.
 
Is there any risk if we probe via? Is it not a standard practice to save space by probing via's during ICT & not providing individual test point on each net?

********* If it is a straight forward via I would not recommend this for a hi-rel application. Vias are not the most robust of things and hitting the via edge with something sharp seems a bit daft. Hitting it more than once due to repeated tests is more than daft. 
 
What precautions need to be taken while using via as a test pad for ICT? What should be the minimum via size and spacing between two vias if they need to be used for probing during the ICT?

********* Minimum spacing between test points should be discussed with you fixture manufacturer. ECT had a very good article showing how successful probing declines as you increase the quantity of probes, reduce probe spacing and reduce target size.
If forced into the situation of having to use vias as test pads (that could not be filled with solder) then we would try to use the minimum probe force and limit retests. 
 
Rgds
Prashant

********* Rex Waygood
Technical Manager
 
Hansatech EMS provides value manufacturing through engineering and quality
 
Hansatech EMS Limited
Benson Road
Nuffield Industrial Estate
Poole
Dorset
BH17 0RY
 
+44 (0)1202 338200
 


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