On 21 Jun 2010 at 16:57, prashant chopra wrote:

> Hi,   Need input regarding the use of vias for probing during the
> ICT process.   Is there any risk if we probe via? Is it not a
> standard practice to save space by probing via´s during ICT & not
> providing individual test point on each net?   What precautions need
> to be taken while using via as a test pad for ICT? What should be
> the minimum via size and spacing between two vias if they need to
> be used for probing during the ICT?   Rgds Prashant 

I use often vias as ICT pads. However, if these vias remain open 
(means not filled with solder) there is a disadvantage especially for 
high volume production: the test needles for these vias hit the hole 
and become "centered" (means: slightly bent) by the hole, thus the 
wear is higher than with needles which just need to hit a more or 
less ductile, flat surface of "standard" ICT pads without hole.

Spacing requirements are the same as with normal test points, but , 
connsider the relation hole size <> minimum size of test tip <> 
minimum spacing between test tips.

If the board is wave-soldered on the ICT pad side, then there is 
normally no problem at all, as the vias are filled with solder and 
then as perfect as "standard" ICT pads without hole >> any type of 
test needle for tinned (=ductile) surfaces will fit.

Best way is, ask your manufacturers what they like or dislike.

Best regards
Matthias


-- 
Matthias Mansfeld Elektronik * Leiterplattenlayout
Neithardtstr. 3, 85540 Haar; Tel.: 089/4620 093-7, Fax: -8
Internet: http://www.mansfeld-elektronik.de
GPG http://www.mansfeld-elektronik.de/gnupgkey/mansfeld.asc


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