Worst part for this is a PIC microcontroller in a QFN package:  The datasheet explicitly says the big paddle beneath is to be a no-connect.  That's a lot of real estate, so it is very tempting to route beneath the part and rely on solder mask to prevent contact.  We get away with this often, but it certainly makes me nervous.  As most users know from bitter experience, soldermask can't be relied on as an insulator.  BUT, it can sometimes perform passable duty as a very thin spacer.  Sounds like just wordplay, but even if there are pinholes in the mask, you will be OK in this situation as long as there are no protuberances on either surface and you don't exceed the voltage stress for arcing.  If forced to do this, I like to put nice big flat pads under the die paddle to make sure there is definitely a nice mask over the copper in these areas.  Again, risky, but with intense inspection of the surfaces, it can work.

Wayne Thayer

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Gerald Gagnon
Sent: Wednesday, June 02, 2010 11:21 AM
To: [log in to unmask]
Subject: [TN] Relying on soldermask as an insulator

Hello Technetters,



From time to time we all probably get asked if it OK to route non-common etch runs underneath components where the only "insulation" preventing etch shorting to the component body is soldermask.



I don't typically advise people to do this type of thing, although I know it is done in practice...usually as a last resort.



Is there any specification out there that either disallows the practice OR allows the practice with certain caveats?



Also, how do the product safety agencies view the practice?



Thanks in advance.



Gerry

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