I don't think this is an entirely rational zone, so data will be ignored as
required.
Personally I think the problem with voiding is that people see a process
variable and confuse that with a functional requirement, not realising that
solder joints are usually well over size for strength and conductivity, and
are arbitrarily sized anyway.
This means even if there were no relationship with reliability/functionality
a large variation in voiding would still be seen as bad. The fact that up
to 75% of the solder joint need not be there is irrelevant to a mind used
to working with and therefore conditioned by plus minus single digit
tolerances/ppm>ppb faults on a line.
Regards
Mike
* Please think before you print
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Inge
Sent: Tuesday, May 04, 2010 2:11 PM
To: [log in to unmask]
Subject: Re: [TN] Question about Voids in Solder Joints
You speak about so and so percentage of voíds in the SJs. Bart Vandevelde
presented, a number of years ago, results from evaluation of solder joint
void in CSP. FC, BGA and the void size vs. strain during temp cycling.
Voids as big as 75 % did not cause significant stress, while a number of
very small voids caused noticable stress, namely, because they were adjacent
to each other, in a row, so as to say. So maybe one stops packages with a
large void and lets go a package with a number of small voids.
Inge
--------------------------------------------------
From: "Bev Christian" <[log in to unmask]>
Sent: den 4 May 2010 14:22
To: <[log in to unmask]>
Subject: Re: [TN] Question about Voids in Solder Joints
> Underway. THAT I will not be able to share.
> Bev
> RIM
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Victor Hernandez
> Sent: Tuesday, May 04, 2010 8:01 AM
> To: [log in to unmask]
> Subject: Re: [TN] Question about Voids in Solder Joints
>
> Was a deep dive conducted on field return fsilure to attribute the
> failure to leaded component voiding?
>
> Victor,
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Bev Christian
> Sent: Monday, May 03, 2010 7:24 PM
> To: [log in to unmask]
> Subject: Re: [TN] Question about Voids in Solder Joints
>
> Thanks, George. Most detailed answer yet.
>
> At Nortel we never had a void spec for leaded components either. And, as
> I
> think I have said on TechNet before, we would find many joints after
> pull
> testing or cross-sectioning that looked like Swiss cheese, but we never
> had
> field failures as a result. BUT we were manly concerned about the
> possibility of failures due to thermal cycling.
>
> Now I worked for a company where the main concern is customers dropping
> their product onto hard edges. We do a lot of work to try and design
> and
> build products to survive multiple drops in different orientations, but
> occasionally a switch is going to come down on a pointed rock or a
> customer
> is going to rip a charging cable out of a connector at a 45 degree angle
> (yikes). These are the things I am talking about. I was leaning
> towards
> 25% for leaded components, so you and I are in the same ball park,
> George.
> Others have suggested a higher number, but without some encouraging
> words in
> that direction from fellow TechNetters, I ain't goin' there.
> Bev
> RIM
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Wenger, George M.
> Sent: Monday, May 03, 2010 5:57 PM
> To: [log in to unmask]
> Subject: Re: [TN] Question about Voids in Solder Joints
>
> Bev,
>
> We're in a similar position to Dave Hillman. We basically follow IPC
> standards (where there are standards). We do not have a company
> standard
> for leaded components. A couple of small voids is okay, more or large
> voids
> are not. Having said that you'll probably ask how many is a couple and
> what
> is small and what is large. We don't have a really good answer. Since
> we
> do a lot of RF power component work we've adopted a voiding
> specification
> that has worked well for IC packages. They typically use a criteria of
> total die attach voids <20% with no single void >5% is okay. We don't
> actually measure voids in leaded devices but if we were to see 20%
> voiding
> in a leaded component solder joint we'd be concerned.
>
> Regards,
> George
> George M. Wenger
> Senior Principal FMA / Reliability Engineer
> Andrew Corporation - Wireless Network Solutions
> 40 Technology Drive, Warren, NJ 07059
> (908) 546-4531 Office (732) 309-8964 Mobile
> E-mail: [log in to unmask]
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Bev Christian
> Sent: Monday, May 03, 2010 3:48 PM
> To: [log in to unmask]
> Subject: [TN] Question about Voids in Solder Joints
>
> TechNetters,
> I was thinking about just putting "Voiding" as the e-mail title, but I
> contemplated what I might get in responses and amended my title
> accordingly.
>
> My question is the following: do any of your companies have upper limits
> on the amount of voiding in SMT solder joints of components that
> customers have access to - like connectors and switches? These of
> course are leaded components. I am not talking about Pb, but the form
> of the interconnect between the component body and the board.
>
> If so, are you willing and can you share?
>
> Bev
> RIM
>
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