Colin,
seen the 'fullchart' I sent to some of you a year ago, with all properties
from nearly all available PWB basic materials? In the column for volume
resistivity after moisture, the spread of data is conspicious. Volume
resistivity spreads magnitudes! In that aspect, selection of board is
crucial. Rogers 4003C seemed to be best choice. Any experience alike?
Inge
--------------------------------------------------
From: "Inge" <[log in to unmask]>
Sent: den 4 May 2010 09:07
To: <[log in to unmask]>
Subject: Re: [TN] Question for High Voltage guru's
> As I've been involved in many q about leakage (we've designed several PWBs
> with many kV WV) I wonder if not there is a close relation between CAF and
> leakage current?
> E.g. NPL MATC(A)155 which reports CAF as and effect of:
>
> - via-to-via gap
> - layout
> - via alignment to glass weave
> - inner layer pads and polarity
> - board surface finish
> -drill feed speed
> - reflow conditions
> - board manufacturing location
> - glass transition temp
> - glass reinforcement
> - laminate chemistry
>
> As I can see it, leakage current is not isolated from CAF.
>
> just a thought
>
> Inge
>
>
>
>
>
>
>
>
> --------------------------------------------------
> From: "Inge" <[log in to unmask]>
> Sent: den 4 May 2010 00:13
> To: "Inge" <[log in to unmask]>; <[log in to unmask]>
> Subject: Re: [TN] Question for High Voltage guru's
>
>>
>> Some guys have contacted me offline to get more about the statement
>> below.
>> It's a factor following Arrhenius's law. I could not promptly find a
>> reference specifically for leakage,
>> but the pasted lines that follow are in principal same for leakage
>> current (and some more ). Agree, very little is written
>> about this in our PWB correspondence, but I'm sure one can find it
>> somewhere in TN's archive.
>> Also, it may also be in Earl Moon's POD Handbook:
>> http://www.dynamixtechnology.com/publications.htm. I got a copy directly
>> from Earl, but I cannot find it for the moment . His handbook is
>> something all should have working with electronics.
>>
>> Inge
>>
>> One cause of temperature related failures of boards or components relates
>> to change or degradation at the molecular level. This type of failure is
>> best modeled as a first order kinetic reaction, typically described as an
>> Arrhenius Equation, which is proportional to the inverse log of the
>> temperature. A simplified Arrhenius equation and a resulting reliability
>> plot against operating temperature are displayed in FIGURE 2. Since
>> failure rates, often described as a mean-time-to-failure (MTTF), increase
>> exponentially with temperature, a 10° C-increase in temperature can
>> double the failure rate. In an operating device where reliability is
>> critical to success, even 1° C can matter. The key to improving
>> reliability is to reduce device temperature by increasing the rate at
>> which heat is removed from the device and from the working area of the
>> PCB immediately adjacent to the device. Understanding heat transfer then
>> becomes the next step.
>>
>>
>> --------------------------------------------------
>> From: "Inge" <[log in to unmask]>
>> Sent: den 3 May 2010 20:34
>> To: <[log in to unmask]>
>> Subject: Re: [TN] Question for High Voltage guru's
>>
>>> Add this : leakage currents double for each 10 Centigrades of
>>> operating temperature
>>>
>>> Inge
>>>
>>> --------------------------------------------------
>>> From: "Paul Edwards" <[log in to unmask]>
>>> Sent: den 3 May 2010 20:01
>>> To: <[log in to unmask]>
>>> Subject: Re: [TN] Question for High Voltage guru's
>>>
>>>> Colin,
>>>>
>>>> How close is the nearest ground in your PCB?
>>>>
>>>> How is the HV routed to the exposed metal pad that I assume is
>>>> Au-plated?
>>>>
>>>> Have built RoHS PCAs with FR-4 type PCB material at +3kv operating and
>>>> found that the leakage path between the HV via and the GND run along
>>>> the glass reinforcing bundles until they plate a circuit and short out
>>>> the HV supply, unless the open air load is a lower resistance path...
>>>>
>>>> Rotate the weave, offset the via grids, bake the laminates and seal the
>>>> PCB...
>>>>
>>>> Paul
>>>>
>>>> Paul Edwards
>>>> Surface Art Engineering
>>>>
>>>> -----Original Message-----
>>>> From: TechNet [mailto:[log in to unmask]] On Behalf Of colin mcvean
>>>> Sent: Monday, May 03, 2010 12:00 AM
>>>> To: [log in to unmask]
>>>> Subject: [TN] Question for High Voltage guru's
>>>>
>>>> Ladies and Gentlemen of Technet-land,
>>>>
>>>> Let's consider an application based on FR4, originally manufactured on
>>>> ceramic base materials:
>>>>
>>>> It generates a plasma field from the surrounding air, neutralizing any
>>>> airborne particals and nasties!
>>>>
>>>> It operates at around 3KV, for a period of time then resets.
>>>>
>>>> Given passivation layers of FR4 are varied dependant on laminate
>>>> suppliers supply-chain at the time of lamination, then what influence
>>>> will this change have? i.e. Would I expect to see any issues with
>>>> different copper suppliers and passivation types?
>>>>
>>>> note: Qualification testing is under load 20% of the time at 3KV under
>>>> 85/85 damp heat conditions for 1000 hours. It has been qualified on
>>>> original FR-4 samples, but now I'm worried about this potential change
>>>> from my laminate supplier.
>>>>
>>>> looking forward as usual to comments and advice
>>>>
>>>> Colin
>>>>
>>>>
>>>>
>>>>
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