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Subject:
From:
"David D. Hillman" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, [log in to unmask]
Date:
Mon, 10 May 2010 11:42:29 -0500
Content-Type:
text/plain
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text/plain (566 lines)
Hi Leland! I am currently in the middle of an investigation on voiding of 
BGAs and CSPs to answer the question you asked. I don't believe that voids 
in solder joints, in general, are a reliability risk but I am conducting 
testing to prove or disprove that belief. Our "round one" effort didn't 
produce the voids necessary for the study (aka voids larger than 25% of 
the pad) but after getting great ideas from the TechNet community, we are 
going to try a second test vehicle build that will hopefully have the 
necessary voids. There are numerous studies on the topic in the public 
domain.

Dave Hillman
Rockwell Collins
[log in to unmask]




Leland Woodall <[log in to unmask]> 
Sent by: TechNet <[log in to unmask]>
05/10/2010 10:38 AM
Please respond to
TechNet E-Mail Forum <[log in to unmask]>; Please respond to
Leland Woodall <[log in to unmask]>


To
[log in to unmask]
cc

Subject
Re: [TN] Question about Voids in Solder Joints






I was just reading last week about a new product that has been designed to 
vacuum voids out of the solder joints immediately after the reflow phase, 
and am wondering if this is truly necessary.  If reflow ovens have to be 
split into sections to allow the insertion of this processing module, 
we're looking at a severe expenditure.

I also have experience with going to AOI systems that identify a cotton 
fiber as a bridge between fine pitch IC leads.  Due to the resolution 
limitations of our automated X-Y inspection stations, the operators cannot 
distinguish this material from a piece of metal.  They wind up being sent 
to Repair, and "contamination" has taken the #1 spot for our SMT defects, 
though in reality, the vast majority have no effect on the product 
reliability.

Then we embark upon the project of totally eliminating dust from our 
process.  Two years later we're still working on it, and I see no way to 
further improve without spending a ton of cash.

Sometimes you just have to take a step back and take a deep breath...

Leland

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Mike Fenner
Sent: Monday, May 10, 2010 10:55 AM
To: [log in to unmask]
Subject: Re: [TN] Question about Voids in Solder Joints

What I am trying to say is, put your self in the mind of someone who is
normally thinking in microns and parts per million. All strictly plus 
minus
small amounts and measurable, can be heaped in statistics. Every thing is
logical and can be categorised.
That is one mindset

Now come to the soldering mind set. This is much more empirical.
First of all the solder joints aren't designed, they are just made. The 
size
is determined by what ever shape the component needs to be and the pads 
are
the size they are because they are, and the amount of solder is what 
works.
What works is what can be made as well as what functions. 
This is not the world of say the first guy.
Now in the world of the soldering guy, the fact that you can have a 75% 
void
is no surprise, and if it works it doesn't matter. To the other mindset 
this
is an uncontrolled variable and must be eliminated.

To explain another way and partly to answer another question in his thread
"when did voids start to matter?" I think we are possibly in the land of
inspection creep. Each time a fault is eliminated the magnifying glass is
made bigger, or we get a more powerful x ray machine and so on.

Many years ago before everything was made an IPC standard I used to advise
customers to take a good assembly from the line and put it in top drawer 
of
desk and lock it. Then a month or three later at the production quality
meetings when people  are complaining about poor quality, to produce it 
and
say 2-3 months ago this was perfect.....


Regards
 
Mike

 
-----Original Message-----
From: Inge [mailto:[log in to unmask]] 
Sent: Tuesday, May 04, 2010 3:11 PM
To: [log in to unmask]; [log in to unmask]
Subject: Re: [TN] Question about Voids in Solder Joints

Mike, can you decifer your high english in the last line, so that a poor 
non- linguistic- elite creature can understand.
Your magniloquence is incommensurable, sir.
 Inge



--------------------------------------------------
From: "Mike Fenner" <[log in to unmask]>
Sent: den 4 May 2010 15:51
To: <[log in to unmask]>
Subject: Re: [TN] Question about Voids in Solder Joints

> I don't think this is an entirely rational zone, so data will be ignored 

> as
> required.
>
> Personally I think the problem with voiding is that people see a process
> variable and confuse that with a functional requirement, not realising 
> that
> solder joints are usually well over size for strength and conductivity, 
> and
> are arbitrarily sized anyway.
>
> This means even if there were no relationship with 
> reliability/functionality
> a large variation in voiding would still be seen as bad.  The fact that 
up
> to 75% of the solder joint need not be there is irrelevant to a mind 
used
> to working with and therefore conditioned by plus minus single digit
> tolerances/ppm>ppb faults on a line.
>
>
>
> Regards
>
> Mike
>
>
> * Please  think before you print
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Inge
> Sent: Tuesday, May 04, 2010 2:11 PM
> To: [log in to unmask]
> Subject: Re: [TN] Question about Voids in Solder Joints
>
> You speak about so and so percentage of voíds in the SJs. Bart 
Vandevelde
> presented,  a number of years ago, results from evaluation of solder 
joint
> void in CSP. FC, BGA and the void size vs. strain during temp cycling.
> Voids as big as 75 % did not cause significant stress, while a number of
> very small voids caused noticable stress, namely, because they were 
> adjacent
>
> to each other,  in a row, so as to say.  So maybe one stops packages 
with 
> a
> large void and lets go a package with a number of small voids.
>
> Inge
>
> --------------------------------------------------
> From: "Bev Christian" <[log in to unmask]>
> Sent: den 4 May 2010 14:22
> To: <[log in to unmask]>
> Subject: Re: [TN] Question about Voids in Solder Joints
>
>> Underway.  THAT I will not be able to share.
>> Bev
>> RIM
>>
>> -----Original Message-----
>> From: TechNet [mailto:[log in to unmask]] On Behalf Of Victor Hernandez
>> Sent: Tuesday, May 04, 2010 8:01 AM
>> To: [log in to unmask]
>> Subject: Re: [TN] Question about Voids in Solder Joints
>>
>> Was a deep dive conducted on field return fsilure to attribute the
>> failure to leaded component voiding?
>>
>> Victor,
>>
>> -----Original Message-----
>> From: TechNet [mailto:[log in to unmask]] On Behalf Of Bev Christian
>> Sent: Monday, May 03, 2010 7:24 PM
>> To: [log in to unmask]
>> Subject: Re: [TN] Question about Voids in Solder Joints
>>
>> Thanks, George. Most detailed answer yet.
>>
>> At Nortel we never had a void spec for leaded components either. And, 
as
>> I
>> think I have said on TechNet before, we would find many joints after
>> pull
>> testing or cross-sectioning that looked like Swiss cheese, but we never
>> had
>> field failures as a result.  BUT we were manly concerned about the
>> possibility of failures due to thermal cycling.
>>
>> Now I worked for a company where the main concern is customers dropping
>> their product onto hard edges.  We do a lot of work to try and design
>> and
>> build products to survive multiple drops in different orientations, but
>> occasionally a switch is going to come down on a pointed rock or a
>> customer
>> is going to rip a charging cable out of a connector at a 45 degree 
angle
>> (yikes).  These are the things I am talking about.  I was leaning
>> towards
>> 25% for leaded components, so you and I are in the same ball park,
>> George.
>> Others have suggested a higher number, but without some encouraging
>> words in
>> that direction from fellow TechNetters, I ain't goin' there.
>> Bev
>> RIM
>>
>> -----Original Message-----
>> From: TechNet [mailto:[log in to unmask]] On Behalf Of Wenger, George M.
>> Sent: Monday, May 03, 2010 5:57 PM
>> To: [log in to unmask]
>> Subject: Re: [TN] Question about Voids in Solder Joints
>>
>> Bev,
>>
>> We're in a similar position to Dave Hillman.  We basically follow IPC
>> standards (where there are standards).  We do not have a company
>> standard
>> for leaded components.  A couple of small voids is okay, more or large
>> voids
>> are not.  Having said that you'll probably ask how many is a couple and
>> what
>> is small and what is large.  We don't have a really good answer.  Since
>> we
>> do a lot of RF power component work we've adopted a voiding
>> specification
>> that has worked well for IC packages.  They typically use a criteria of
>> total die attach voids <20% with no single void >5% is okay. We don't
>> actually measure voids in leaded devices but if we were to see 20%
>> voiding
>> in a leaded component solder joint we'd be concerned.
>>
>> Regards,
>> George
>> George M. Wenger
>> Senior Principal FMA  / Reliability Engineer
>> Andrew Corporation - Wireless Network Solutions
>> 40 Technology Drive, Warren, NJ 07059
>> (908) 546-4531 Office (732) 309-8964 Mobile
>> E-mail: [log in to unmask]
>> -----Original Message-----
>> From: TechNet [mailto:[log in to unmask]] On Behalf Of Bev Christian
>> Sent: Monday, May 03, 2010 3:48 PM
>> To: [log in to unmask]
>> Subject: [TN] Question about Voids in Solder Joints
>>
>> TechNetters,
>> I was thinking about just putting "Voiding" as the e-mail title, but I
>> contemplated what I might get in responses and amended my title
>> accordingly.
>>
>> My question is the following: do any of your companies have upper 
limits
>> on the amount of voiding in SMT solder joints of components that
>> customers have access to - like connectors and switches?  These of
>> course are leaded components.  I am not talking about Pb, but the form
>> of the interconnect between the component body and the board.
>>
>> If so, are you willing and can you share?
>>
>> Bev
>> RIM
>>
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