Thanks Kevin.

To all PCB designers,

Appreciate if you could provide some information on the solder mask
clearance/opening for test points based on past collected experience.
With this information, I would like to benchmark the industrial
practice/standard used before quantify into some reference. Thank you.
 
Cheers!


-----Original Message-----
From: Glidden, Kevin [mailto:[log in to unmask]] 
Sent: Tuesday, January 05, 2010 9:36 PM
To: TechNet E-Mail Forum; Gobinathan Athimolom
Subject: RE: [TN] Minimum Solder Masking on Test Point and Vias

IPC-CM-770 has some information regarding location, size, and spacing of
test points for automated testing.  It does not specify (that I can
tell) a definitive soldermask clearance requirement for testpoints.  In
that regard, I guess it is up to the designer to specify a clearance
that will provide sufficient protection between test points and adjacent
lands, but not encroach the minimum test point dia / land size.  In that
regard, couldn't you also specify soldermask defined lands for test
points?  There would be no clearance then....

-----Original Message-----
From: Gobinathan Athimolom [mailto:[log in to unmask]] 
Sent: Tuesday, January 05, 2010 2:06 AM
To: [log in to unmask]
Subject: [TN] Minimum Solder Masking on Test Point and Vias

Hi folks!

What is an ideal or a rule of thumb for solder mask opening on test
point or via 
for PCB? Let say the test point/via copper diameter is 0.5mm, what is a 
recommended solder mask opening? 

Is there an IPC standard for solder mask opening for test point and via?
Mainly 
for accessibility using in-circuit (bed-of-nail) test approach. 

Appreciate any kind of inputs. Thanks.

Cheers!
Gobi

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