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January 2010

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From:
Dwight Mattix <[log in to unmask]>
Date:
Mon, 4 Jan 2010 15:50:29 -0800
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TechNet E-Mail Forum <[log in to unmask]>, Dwight Mattix <[log in to unmask]>
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>
>question regarding plated closed vias: I have the same concern Paul just
>mentioned. Is there not a reliability concern with trapped contaminants in
>the via when plating closed? I stopped spec-ing minus tol same as via dia.
>because of this.

Yes.  Been there, done that, got the t-shirt.

However, there are some very few fabs now who've managed to adapt the 
new-fangled filled copper uVia processes (e.g. Shipley's uFill) to 
fill small thru vias completely and reliably.

>Happy 2010,
>-Chris
>
>
>
>
>
>              "Brooks, Bill"
>              <[log in to unmask]
>              >                                                          To
>              Sent by: TechNet          [log in to unmask]
>              <[log in to unmask]>                                          cc
>
>                                                                    Subject
>              01/04/2010 02:47          Re: [TN] Thermally Conductive &
>              PM                        Plated Via Fill
>
>
>              Please respond to
>               TechNet E-Mail
>                    Forum
>              <[log in to unmask]>
>              ; Please respond
>                     to
>               "Brooks, Bill"
>              <[log in to unmask]
>                      >
>
>
>
>
>
>
>
>Randy,
>
>There are some things that defy logic and reason... and are often done
>without the proper science. I'm sure there are many reasons 'why'. I
>won't try to guess at them. Do you remember soldermask over solder
>plated finish for double sided boards and what that produced? A real
>mess after the board was heated to solder the parts... but board
>manufacturers did it anyway... because it was on the print... go
>figure...
>
>Tin/lead solder is a poor conductor of heat compared to copper... So in
>thermal applications we increase the thickness of the via barrel from
>1oz to  2-3oz copper to get better thermal conductivity through the vias
>to the back side of the board where we can put a thermal pad to the
>chassis if needed.
>
>Some folks don't think beyond the transfer of heat to the board... and
>forget to make a path for that heat to the ambient air... which is a
>mistake they will discover later when they test the unit over temp. Just
>pumping heat into the board is not always a complete solution. Depending
>upon thermal transfer thru solder filled vias doesn't make sense either.
>
>Solder filling of exposed thermal vias that are in large 'belly pad'
>designs is really unavoidable at assembly but not a significant or
>useful part of the equation for thermal transfer...
>
>The cross sectional area of that copper is modeled for thermal
>applications. The more copper the better for conductivity. We use very
>small diameter via thru holes and allow them to plate shut if possible.
>Whatever solder gets into them is incidental not intentional. Solid
>copper plating thru the board would be the best condition... but it
>costs more. So far we have not had any problems with this current design
>concept The small diameter vias tend to rob less solder from the belly
>pad producing a partially filled via due to the capillary action of the
>solder... we typically use solder with lead in it... lead free solder
>may not wick into the holes quite so easily as it has a different
>surface tension.
>
>The idea of 'plugging vias with solder' as a pre-assembly step seems
>unwise to me too for the logical reasons you have already presented.
>
>I will be curious to hear any arguments to the contrary...
>
>Best regards,
>
>Bill Brooks | Datron World Communications, Inc.
>PCB Designer/Engineer | Office: 760-602-7004| Fax: 760-597-3777 |
>[log in to unmask]
>1808 Aston Avenue, Suite 230, Carlsbad, CA 92008 | www.dtwc.com
>
>Performance You Require. Value You ExpectTM
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Randy
>Sent: Monday, January 04, 2010 7:56 AM
>To: [log in to unmask]
>Subject: Re: [TN] Thermally Conductive & Plated Via Fill
>
>Can someone please help me break my paradigm with "filling vias in
>process with solder"?  I have difficulty seeing how this works.  How do
>you ensure consistent, predictable solder fill in thermal vias during
>assembly?  If inconsistent, then you really can't count on it to be
>there
>since any time it's not there you'll pay for it.
>
>If by some chance you can get solder to fill all vias completely, then
>how do you avoid solder flowing out the opposite end of the vias?
>Protruding solder "bumps" can interfere with solder paste printing if
>bottom (second) side assembly is required.  These solder "bumps" can
>also interfere with heat sinking if intimate contact is required in this
>
>area for heat dissipation.
>
>Regards,
>Randy
>
>
>On Tue, 29 Dec 2009 12:28:35 -0800, Dwight Mattix
><[log in to unmask]> wrote:
>
> >Practically speaking, using "thermal conductive" and "CB100" in the
> >same sentence is an oxymoron.
> >
> >
> >Cu ~= 300 w/mK
> >Solder, Ormet, et al ~= 25 w/mk
> >CB100 ~=3 w/mK
> >
> >Small amount more annular copper, filling with Ormet paste (not a
> >cheaper option though) or filling via in process with solder yields
> >much greater increase in thermal conductivity than CB100.
> >
> >At 11:55 AM 12/29/2009, Joe Lara wrote:
> >>Hello TechNetter's,
> >>
> >>Im currently using Du Ponts "CB-100" Conductive Paste to vill Vias
> >>at $400 per 100G. Is
> >>there a more affordable way of filling vias that call out to be
> >>filled (thermal conductive) and
> >>plated?
> >>
> >>
> >>Best Regards,
> >>
> >>Joe
> >>
>
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