Hi Alejandro,
Bev reads me like a book—what he said is true. And it is also true that macro-voids of the type described do not significantly impact creep-fatigue reliability either.
Werner

 

 

-----Original Message-----
From: Bev Christian <[log in to unmask]>
To: [log in to unmask]
Sent: Sat, Nov 7, 2009 10:59 am
Subject: Re: [TN] Solder Voids in Chip Components










Alejandro,
No there is not. 

In the 10 years I was at Nortel we could never see any significant difference 
between shear strength of solder joints with low voiding and those that looked 
like Swiss cheese (up to 50% voiding). I am sure that Werner will come back and 
rightly say that shear strength does not necessarily equate to solder joint 
reliability. But I can say we never saw chip cap problems that were traceable to 
the joint voids. 
Bev

----- Original Message -----
From: TechNet <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Sent: Sat Nov 07 10:40:25 2009
Subject: [TN] Solder Voids in Chip Components

Hello,

Does anybody know if there is an IPC specification that describes the amount of 
solder voids allowed in a chip component solder joint?  The IPC-A-610 Rev D is 
specific describing the % of voids allowed for BGA's solder joints (<25%) only 
but not for any other type of components.     

Saludos Cordiales / Best Regards 
Alejandro A. Domínguez 
Robert Bosch Corporation



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