John,

None of the photos makes sense in relations to pits and void. Last photo
for nonconforming show a pit/damage in solder mask not in dielectric...

Mahendra Gandhi 

-----Original Message-----
From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of John Perry
Sent: Thursday, November 05, 2009 3:29 PM
To: [log in to unmask]
Subject: [IPC-600-6012] IPC-A-600 Revision H Imagery - Pits and Voids

Hi All,

Most of you are familiar with the ongoing effort to resolve comments to
the Final Draft circulation of IPC-6012C, and while that is nearing
completion, I want to get started on addressing comments received to the
Final Draft circulation of IPC-A-600H through this task group e-mail
forum.

Section 2.2.4 of the IPC-A-600H Final Draft (located at
http://www.ipc.org/CommitteeDetail.aspx?Committee=7-31A under "Drafts")
addresses pits and voids in printed board base material.

Figure 224c under "Acceptable - Class 1, 2, 3" is new to Revision H, but
received a number of comments indicating that the figure is confusing -
it's not clear what the yellow arrow is pointing to and pits and voids
are not evident.

Does anyone have a better photograph that shows an acceptable degree of
pits and voids on a printed board surface?

Thanks,

John Perry
Technical Project Manager
IPC - Association Connecting Electronics Industries(r)
3000 Lakeside Drive # 309S
Bannockburn, IL 60015-1249 USA
+1 847-597-2818 (tel)
+1 847-615-7105 (fax)
+1 847-615-7100 (Main)
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