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November 2009

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Mon, 9 Nov 2009 09:50:19 -0800
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"(Designers Council Forum)" <[log in to unmask]>, "Brooks, Bill" <[log in to unmask]>
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Please RSVP and join us for:
 SD Designer Council presentation on Boundary Scan Test Fundamentals w/ Design and Layout Considerations
November 17th for dinner, socializing and a presentation! Please see description at bottom.
We will meet at Hallmark Circuits in San Diego.

6-7:30PM, Tuesday Nov.17  
                                                                                                                        Hosted by: SDDC of the IPC at Hallmark Circuits

This meeting will take place at:
Hallmark Circuits
13500 Danielson
Poway, CA 92064 

See Google map for directions:
http://maps.google.com/maps?f=q&source=s_q&hl=en&geocode=&q=hallmark+circuits&sll=37.0625,-95.677068&sspn=47.033113,113.818359&ie=UTF8&hq=hallmark+circuits&hnear=&ll=32.938674,-117.02877&spn=0.097966,0.222301&z=13
 

Topic:      Boundary-Scan Test Fundamentals Including Design and Layout Considerations

Implementing boundary-scan into your printed circuit board designs
Presentation by:  Ryan Jones - Senior Technical Marketing Engineer - Corelis, Inc

The inability to test highly complex and dense PC boards using traditional in-circuit testers and bed-of-nail fixtures was already evident in the mid-eighties. With the continued miniaturization of integrated circuits, higher board densities, and limited test point access, boundary-scan offers a means of solving these issues. This presentation provides a brief overview of the boundary-scan architecture and the new technology trends that make using boundary-scan essential. Design guidelines for successfully implementing boundary-scan on a printed circuit board will also be covered.

Ryan brings 15 years of experience in the test equipment industry. He started his career as a design engineer developing measurement electronics and writing firmware for bare board test equipment including flying probers.  Now focusing more on loaded board testing, Ryan has become an expert in the field of boundary-scan testing and provides seminars and training classes throughout the globe.

Corelis, Inc., a subsidiary of Electronic Warfare Associates, Inc., offers bus analysis tools, embedded test tools, and the industry's broadest line of JTAG/boundary-scan software and hardware products combining exceptional ease-of-use with advanced technical innovation and unmatched customer service. Corelis' development and test tools are used by companies such as Agilent, Dell, IBM, Jabil, Intel, Microsoft, Lockheed Martin, Rockwell Collins, Hewlett-Packard, Motorola, Qualcomm, Nokia, Panasonic, TI, Ford, Plexus, Broadcom, Ericsson, Flextronics, and many others. Corelis products are found globally in every industry developing or manufacturing electronic products.

Please contact Ben Savage, SDDC Communications Officer to RSVP by November 16th and ask any questions (619)820-7810 [log in to unmask]

We will provide dinner and beverages. This discussion is free to IPC Designers Council members, a $5 donation is optional for non-members. The $5 donation can be applied to membership dues if attendee wishes to become a member.
*If you do not wish to receive future notices please respond to this e-mail with "unsubscribe" in the subject bar*

Ben R. Savage
Sales & Service Engineer
Winonics- Brea, CA
Cosmotronic- Irvine, CA
Bench2Bench- Fullerton, CA
Office 714-256-8700
Fax 714-256-8706
Cell 619-820-7810

Send Commercial RFQ's and Data to [log in to unmask] Winonics 714-256-8700
Send Military & Aerospace RFQ's to [log in to unmask] Cosmotronic 949-660-0740
Send Ultra High Density Interconnects (UHDI) RFQ's to [log in to unmask] Bench2Bench 714-626-3755

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