Sorry this would be bad practice. We all know that this practice would be
variable using different small vias. 

We all know that the solderability of different surface finish will vary
hence the degree the solder will wick away. What you want is a stable
process. I would suggest the company is using too much paste in the first
place on the centre pad.

Just built a batch of boards yesterday using resist ringed vias and slit
print apertures on the centre pad. If people would like to see the
comparison I can send results after x-ray on Tuesday.

I sent this link on QFNs previously which may be of interest suggesting this
method.

http://blog.ipc.org/2009/08/14/successful-soldering-180-pin-qfn/ 

Many thanks


Bob Willis
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
Tel: (44) 1245 351502
Fax: (44) 1245 496123
Mobile: 07860 775858
www.ASKbobwillis.com
www.SolderingStandards.com 
New Package on Package Workshops 24th November
www.ASKbobwillis.com/PoPWorkshops.pdf 
PCB Inspection & Quality Control Workshop 3rd November
www.ASKbobwillis.com/faworkshops.pdf
Book Bob's "Step by Step Failure Analysis
Workshop"4th November  www.ASKbobwillis.com/faworkshops.pdf
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www.ASKbobwillis.com/PoPWorkshops.pdf


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Tom Sylla
Sent: 29 October 2009 19:12
To: [log in to unmask]
Subject: [TN] Simple QFN style question

I am a PCB design engineer, and we have been getting conflicting
requests from our assembly houses regarding thermal pad styles. I am
hoping some technetter assembly folks can give some guidance as to
good practices for reliable mounting.

This part is a good example of the type of part in question:
http://www.linear.com/designtools/packaging/qfn/UHF38.pdf

In general, for most thermal pads we create our footprint matching the
recommended solder pad layout, and the stencil house windows the paste
appropriately for correct mounting. (the vias connecting the pad to
planes are outside of the thermal pad boundary of the part)

Our PCB assembly company we use for production in Japan has not had
any problems with this, and our QFN-style parts have mounted fine on
many different boards.

We have been using a local (US) assembly company to do our prototypes,
and we have been getting some conflicting requests from them. They
have requested that we add vias to the thermal pad, not for thermal
sinking reasons, but to "wick" away extra solder to make the parts
settle properly. In the spectrum of modifications to a thermal pad,
this sort of sounds like the worst case. Some web evidence seems to
agree with that:
http://blog.screamingcircuits.com/2009/01/speaking-of-common-qfn-issues.html

Our understanding has been that in the best case for vias in the
thermal pad they should be plated shut or otherwise plugged (coplanar
with the pad). Another option would be to window the paste as to not
overlap the vias (we have seen various app notes from IC vendors
suggesting this strategy) but that is still risky.

What is the correct answer? We have been going on the standard of
trusting the assembly company, and doing what they have qualified as
good practice, but we are at a point where the recommendations
conflict.

Thanks for any suggestions,
Tom

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