TECHNET Archives

October 2009

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Inge <[log in to unmask]>
Date:
Thu, 29 Oct 2009 20:55:43 +0100
Content-Type:
text/plain
Parts/Attachments:
text/plain (118 lines)
Graham,
why surprised? We have practised 'near-toe' vias for reducing solder wicking 
for many years. Indeed very smart. Important to make a design that differs 
from ordinary vias, because  not used such vias may cause wetting to oposite 
side.  In such cases the vias must be selead with e.g epoxy. Works like kind 
of reservoir. Does not work for very thick boards.
/Inge


----- Original Message ----- 
From: "Graham Collins" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, October 29, 2009 8:29 PM
Subject: Re: [TN] Simple QFN style question


I'm a bit baffled (and it sounds like you are) at the request "add vias
to the thermal pad, not for thermal sinking reasons, but to "wick" away
extra solder to make the parts settle properly"...

If there is too much solder there to allow the parts to settle properly,
why wouldn't they tweak their stencil design?  A solution where you are
relying on vias to wick solder away is not one I would suggest or
support as reasonable.  Too much variability between boards, etc...

Our QFN layouts do not use vias in the pads.

regards,
 - Graham

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Tom Sylla
Sent: Thursday, October 29, 2009 4:12 PM
To: [log in to unmask]
Subject: [TN] Simple QFN style question

I am a PCB design engineer, and we have been getting conflicting
requests from our assembly houses regarding thermal pad styles. I am
hoping some technetter assembly folks can give some guidance as to
good practices for reliable mounting.

This part is a good example of the type of part in question:
http://www.linear.com/designtools/packaging/qfn/UHF38.pdf

In general, for most thermal pads we create our footprint matching the
recommended solder pad layout, and the stencil house windows the paste
appropriately for correct mounting. (the vias connecting the pad to
planes are outside of the thermal pad boundary of the part)

Our PCB assembly company we use for production in Japan has not had
any problems with this, and our QFN-style parts have mounted fine on
many different boards.

We have been using a local (US) assembly company to do our prototypes,
and we have been getting some conflicting requests from them. They
have requested that we add vias to the thermal pad, not for thermal
sinking reasons, but to "wick" away extra solder to make the parts
settle properly. In the spectrum of modifications to a thermal pad,
this sort of sounds like the worst case. Some web evidence seems to
agree with that:
http://blog.screamingcircuits.com/2009/01/speaking-of-common-qfn-issues.
html

Our understanding has been that in the best case for vias in the
thermal pad they should be plated shut or otherwise plugged (coplanar
with the pad). Another option would be to window the paste as to not
overlap the vias (we have seen various app notes from IC vendors
suggesting this strategy) but that is still risky.

What is the correct answer? We have been going on the standard of
trusting the assembly company, and doing what they have qualified as
good practice, but we are at a point where the recommendations
conflict.

Thanks for any suggestions,
Tom

---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 15.0
To unsubscribe, send a message to [log in to unmask] with following text
in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to
[log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
Search the archives of previous posts at:
http://listserv.ipc.org/archives
Please visit IPC web site
http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100
ext.2815
-----------------------------------------------------

---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 15.0
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to 
[log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to 
[log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 
for additional information, or contact Keach Sasamori at [log in to unmask] or 
847-615-7100 ext.2815
----------------------------------------------------- 

---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 15.0
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
-----------------------------------------------------

ATOM RSS1 RSS2