If they're not also needed overplated for probing purposes then we
prefer non-conductive fill (w/ 100% solids paste), planarize and
final finish. Fab's don't like it so before final finish much but
doing it earlier in the process tends to reduce problems with epoxy
residues on solderable surface affecting solderability.
At 11:55 AM 9/28/2009, you wrote:
>Of course it works. The only time it is an issue is when the buildup of
>soldermask is so high that you get excess solder joints on the chip caps
>and resistors. IC network resistors are not an issue. The issue on the
>connectors can also be resolved by working with the PWB vendor to keep
>the masking to a minimum over the vias.
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Leif Erik Laerum
>Sent: Monday, September 28, 2009 1:29 PM
>To: [log in to unmask]
>Subject: Re: [TN] Plug vias first or second.
>
>Thank you for the input. I see your point, but in our case we are
>talking about resistor and capacitor networks. These have 10 mil pads
>and 20 mil pitch. There are no vias under the component nor between
>pads. It is not possible from a design perspective to move the vias far
>enough from component to allow proper gasketing. We also have a fine
>pitch SMT connector with 20 mil pitch. There are center pads on these
>onnected to the ground plane. This is where the vias are that cause the
>issue. I must have the vias here to connect to the plane. DFM.... I
>know...We have other boards from other vendors with the same design so
>this should work as long as the PCB vendor has a good process and is
>given correct and manageable parameters.
>
>Leif Erik Laerum
>Quality Assurance Manager
>Texas Memory Systems
>[log in to unmask]
>Tel: (713) 266-3200 x468
>www.texmemsys.com
>
>
>
>Stadem, Richard D. wrote:
> > I posted a number of reasons that the vias should not be designed in
>between the pads on this forum awhile back. Many responded with
>"likewise" comments. Inability to gasket the stencil flat to the PWB was
>just one of a list of issues it creates.
> >
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]] On Behalf Of stephen gregory
> > Sent: Monday, September 28, 2009 12:45 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] Plug vias first or second.
> >
> > Hi Leif,
> >
> > I've run across the same issue in the past. One way to get around the
>bumps is to have your stencil vendor half etch all the vias into the
>bottom of the stencil. I've had to do that a few times...
> >
> > Steve
> >
> > --- On Mon, 9/28/09, Leif Erik Laerum <[log in to unmask]>
>wrote:
> >
> >
> > From: Leif Erik Laerum <[log in to unmask]>
> > Subject: [TN] Plug vias first or second.
> > To: [log in to unmask]
> > Date: Monday, September 28, 2009, 11:03 AM
> >
> >
> > Technetters,
> >
> > We have a problem with certain PCBs where plugged vias have a solder
>mask "mound" that creates a coplanarity issues and also causes the
>screen to be elevated. The elevated screen results in excessive solder
>deposit and massive amount of shorts for the finest pitch parts. We
>believe the root cause is the practice of plugging the vias with solder
>mask after they have been covered. This seems to result in these mounds
>instead of a planar surface. From what we understand, this is the
>preferred order of the two steps by PCB vendors.
> >
> > Why is this preferred?
> > Is there a IPC spec that covers this issue?
> > Is it reasonable to specify that the plugging must result in no mounds
>and 0 elevation of the vias?
> > Is there a particular process weakness from the PCB vendors that
>causes this defect?
> >
> > Thank you.
> >
> > -- Leif Erik Laerum
> >
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