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September 2009

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Subject:
From:
Robert Kondner <[log in to unmask]>
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Date:
Mon, 28 Sep 2009 14:16:13 -0400
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Hi,

  What kind of distance would be required between via and SMT pad to
reduce/eliminate the stencil gasket issues?

Assume a 5 mil stencil?

Thanks,
Bob Kondner

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Stadem, Richard D.
Sent: Monday, September 28, 2009 2:06 PM
To: [log in to unmask]
Subject: Re: [TN] Plug vias first or second.

I posted a number of reasons that the vias should not be designed in between
the pads on this forum awhile back. Many responded with "likewise" comments.
Inability to gasket the stencil flat to the PWB was just one of a list of
issues it creates.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of stephen gregory
Sent: Monday, September 28, 2009 12:45 PM
To: [log in to unmask]
Subject: Re: [TN] Plug vias first or second.

Hi Leif,
 
I've run across the same issue in the past. One way to get around the bumps
is to have your stencil vendor half etch all the vias into the bottom of the
stencil. I've had to do that a few times...
 
Steve

--- On Mon, 9/28/09, Leif Erik Laerum <[log in to unmask]> wrote:


From: Leif Erik Laerum <[log in to unmask]>
Subject: [TN] Plug vias first or second.
To: [log in to unmask]
Date: Monday, September 28, 2009, 11:03 AM


Technetters,

We have a problem with certain PCBs where plugged vias have a solder  mask
"mound" that creates a coplanarity issues and also causes the screen to be
elevated. The elevated screen results in excessive solder deposit and
massive amount of shorts for the finest pitch parts. We believe the root
cause is the practice of plugging the vias with solder mask after they have
been covered. This seems to result in these mounds instead of a planar
surface. From what we understand, this is the preferred order of the two
steps by PCB vendors.

Why is this preferred?
Is there a IPC spec that covers this issue?
Is it reasonable to specify that the plugging must result in no mounds and 0
elevation of the vias?
Is there a particular process weakness from the PCB vendors that causes this
defect?

Thank you.

-- Leif Erik Laerum

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