Leif,

IPC-4761, "Design Guide for Protection of Printed Board Via Structures" is
the document to reference in this regard.  I am not sure that I would say
that plugging vias after the application of the final finish is preferred by
PCB vendors but it is felt by many, and recommended by IPC-4761 that
plugging prior to final finish application can result in interconnect
failures as a result of trapped chemistry.  My personal opinion is that the
risk of this type of failure is somewhat of a perfect storm but it is
certainly difficult to argue the 'better safe than sorry' stance on this
matter.

Although I am not sure it is a documented value, others can correct me if I
am wrong, I think the accepted value for the maximum thickness of solder
mask over the surface plating is 3 mil (0.003").  If your mask is thicker
than this then your vendor should hopefully be able to do better.

John Parsons
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Leif Erik Laerum
Sent: Monday, September 28, 2009 9:03 AM
To: [log in to unmask]
Subject: [TN] Plug vias first or second.

Technetters,

We have a problem with certain PCBs where plugged vias have a solder  
mask "mound" that creates a coplanarity issues and also causes the 
screen to be elevated. The elevated screen results in excessive solder 
deposit and massive amount of shorts for the finest pitch parts. We 
believe the root cause is the practice of plugging the vias with solder 
mask after they have been covered. This seems to result in these mounds 
instead of a planar surface. From what we understand, this is the 
preferred order of the two steps by PCB vendors.

Why is this preferred?
Is there a IPC spec that covers this issue?
Is it reasonable to specify that the plugging must result in no mounds 
and 0 elevation of the vias?
Is there a particular process weakness from the PCB vendors that causes 
this defect?

Thank you.

-- 
Leif Erik Laerum

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