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Subject:
Re: Ground Pour Under BGA
From:
Dwight Mattix <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Dwight Mattix <[log in to unmask]>
Date:
Wed, 16 Sep 2009 08:51:58 -0700
Content-Type:
text/plain
Parts/Attachments:
text/plain (298 lines) 
At 08:23 AM 9/16/2009, Robert Kondner wrote:
>Ken,
>
>   I don't know your total stack up but having internal layers between GND
>and PWR planes is waste of planes.

or not.   though that is my bias too.


>  Plane pairs are SO much more effective
>when they are very close.

depending on thickness budget and sig integrity rqmts this can be a 
waste of overall thickness/reduce total available routing layers.

As always -- it depends. :-)

>Putting routing layers in between is not good.
>
>  People sometimes imaging they are putting traces inside a faraday cage when
>they do that but it is a false assumption.
>
>Bob Kondner
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Kenneth Wood
>Sent: Wednesday, September 16, 2009 10:27 AM
>To: [log in to unmask]
>Subject: Re: [TN] Ground Pour Under BGA
>
>You're not routing below the GND plane, you are routing below the PWR
>plane(s)...maybe on layer 3 or 4 or 5 etc...
>
>Ken
>
>Saturn PCB Design, Inc.
>www.saturnpcb.com
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner
>Sent: Wednesday, September 16, 2009 10:23 AM
>To: [log in to unmask]
>Subject: Re: [TN] Ground Pour Under BGA
>
>Hi,
>
>   But that still makes your top GND plane look like Swiss Cheese. When I
>think of routing below that "Swiss Chese" and the return currents moving
>around all thoses holes it gives me the Creeps.
>
>   Where did I go wrong?
>
>Bob Kondner
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Kenneth Wood
>Sent: Wednesday, September 16, 2009 10:17 AM
>To: [log in to unmask]
>Subject: Re: [TN] Ground Pour Under BGA
>
>Keep in mind that on HDI designs you are not JUST adding a few micro vias
>and pouring GND on the top layer...you are using via-in-pad
>on all devices so to try and minimize top side pour cuts. Also, you are
>routing as many nets on internal layers as possible.
>The top layer GND is not usually the only GND plane too, there is usually an
>internal plane to back up the top layer.
>This does reduce EMI significantly, shorter runs and external shielding
>works.
>Ken
>Saturn PCB Design, Inc.
>www.saturnpcb.com
>
>
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner
>Sent: Wednesday, September 16, 2009 10:07 AM
>To: [log in to unmask]
>Subject: Re: [TN] Ground Pour Under BGA
>
>Ken,
>
>   With all the BGA pads and possible vias I don't see how a top side can
>have a better mesh of copper paths than an internal layer. I would think a
>poor copper mesh plane would be a generator of large GND return loops. Aka
>antennas.
>
>  As for a GND plane being a few mils closer to the BGA and this reducing
>EMI, that sounds like hog wash. Consider that conductor lengths from a ball
>to chip is probably about 1/2 inch at times. How is adding 10 mils going to
>affect anything?
>
>  I am open to Hog Wash ideas but they need to be well defined.
>
>Thanks,
>Bob Kondner
>
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Kenneth Wood
>Sent: Wednesday, September 16, 2009 9:54 AM
>To: [log in to unmask]
>Subject: Re: [TN] Ground Pour Under BGA
>
>It is an technique used in HDI designs that utilize micro vias.
>Top layer is GND and layer 2 can be a power layer. It also helps with EMI.
>Ken
>Saturn PCB Design, Inc.
>www.saturnpcb.com
>
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner
>Sent: Wednesday, September 16, 2009 8:42 AM
>To: [log in to unmask]
>Subject: Re: [TN] Ground Pour Under BGA
>
>Hi,
>
>   What would be the goal of placing atop side GND plane under the BGA?
>
>   Low Z Gnd return? Electrostatic shield?
>
>   Having a plane under the BGA vs another layer is not going to make a
>difference in plane Z.
>
>  Sounds like a good chance of creating shorts if the solder mask chips or is
>damaged during rework.
>
>Bob Kondner
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Guy Ramsey
>Sent: Wednesday, September 16, 2009 7:43 AM
>To: [log in to unmask]
>Subject: Re: [TN] Ground Pour Under BGA
>
>IPC 7095, BGA Technology by Lau.
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Toby Carrier
>Sent: Tuesday, September 15, 2009 8:45 PM
>To: [log in to unmask]
>Subject: [TN] Ground Pour Under BGA
>
>Hello all,
>
>Is it a good idea to create a top layer ground flood under a BGA package? I
>am
>guessing that the fanout will not allow much area for the ground pour, am I
>correct in thinking so? Does anyone have any good reference info on this
>topic?
>
>Also, if you don't have a ground pour under the BGA, how will that affect
>the
>impedance control of the traces going to the BGA ball?
>
>Thanks for the help,
>
>Toby
>
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