There was good EMC research done about 5-7 years ago at the University of
Missouri-Rolla (UMR - now Missouri University of Science and Technology)
that investigated this design technique and explained how, why, and when it
might be helpful. I know it is tempting sometimes to dismiss seemingly
weird or useless PCB EMC design techniques out-of-hand, but there are a lot
of smart people around the world spending a lot of time doing mathematical,
computational, and experimental research work to analyze, understand, and
prove the usefulness or uselessness of many different aspects of PCB design.
For this specific example, the basic idea is to encourage capacitive
coupling from the top of the IC back down to the "low side of the source",
which in general is the "ground plane" of the PCB. For it to be perceived
as effective, many conditions must be met 1) the IC must be troublesome
source of E field coupling, 2a) there must be a "victim" of the E field
coupling, and 2b) the victim is sensitive enough or the regulatory emissions
limit low enough that the noise coupling is troublesome. "plane impedance"
is a little vague, it is not clear whether this refers to power bus
impedance (then there must be a second power conductor somewhere), or just
the impedance of the ground plane(s) alone, which is not defined without
first defining a complete signal or noise loop geometry. If we have a PCB
where there already is a "ground" plane at layer 2, then there probably is
not as much benefit to the technique for noise control. I think the research
was spurred by the use of 4 or 6 layer boards, where the IC might not
"normally" have a "ground" plane directly beneath it.
Best Regards
Lee UMR '92
Lee Hill
SILENT
10 Northern Boulevard, Suite 1
Amherst, NH 03031
USA
+1 (603) 578-1842 (v)
+1 (603) 578-1843 (f)
+1 (508) 341-3947 (m)
[log in to unmask]
Electromagnetic Compatibility and RF Design, Troubleshooting and Training
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner
Sent: Wednesday, September 16, 2009 8:42 AM
To: [log in to unmask]
Subject: Re: [TN] Ground Pour Under BGA
Hi,
What would be the goal of placing atop side GND plane under the BGA?
Low Z Gnd return? Electrostatic shield?
Having a plane under the BGA vs another layer is not going to make a
difference in plane Z.
Sounds like a good chance of creating shorts if the solder mask chips or is
damaged during rework.
Bob Kondner
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Guy Ramsey
Sent: Wednesday, September 16, 2009 7:43 AM
To: [log in to unmask]
Subject: Re: [TN] Ground Pour Under BGA
IPC 7095, BGA Technology by Lau.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Toby Carrier
Sent: Tuesday, September 15, 2009 8:45 PM
To: [log in to unmask]
Subject: [TN] Ground Pour Under BGA
Hello all,
Is it a good idea to create a top layer ground flood under a BGA package? I
am
guessing that the fanout will not allow much area for the ground pour, am I
correct in thinking so? Does anyone have any good reference info on this
topic?
Also, if you don't have a ground pour under the BGA, how will that affect
the
impedance control of the traces going to the BGA ball?
Thanks for the help,
Toby
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