Victor,

I am not sure what the IPC equivalent to MIL-STD-883 would be, but if you
refer to 883, TM 2010 - internal visual - monolithic, or TM 2017 internal
visual - hybrid you may find what you are looking for.

My recollection is that TM 2010 may provide the most info [para 3.1.3]
although we were mostly concerned about chip-outs at the upper edge of the
chip, nearer to the active region.  You might consider the section on flip
chips for info as well.

If the chips are diced with a diamond saw, one seldom [if ever] sees
chipping along the bottom edge of the die unless there has been mis-handling
of the sawn wafer while still on the frame.  Mainly, don't want cracks going
in the direction of the active region of the chip - [personally, don't want
to see cracks AT ALL - especially, if you can see them with a low-power
scope, etc].

We would not want to see loose bits of Si rattling around inside a sealed
hybrid.  If over-molded, it is not so likely to move anywhere...

Interested in further detail of the chipping you are seeing.

You should be able to down-load MIL-STD-883G from
http://assist.daps.dla.mil/online/start/
Once you get the user sign-on info.  It is a ~6 Mb file

Steve


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Victor Hernandez
Sent: Wednesday, August 05, 2009 8:16 AM
To: [log in to unmask]
Subject: [TN] die base chip outs / fractures

Fellow TechNetters:

   Is there an IPC documents pertaining to acceptance of anomalies with
die.   I am see small cracks/chip out at the die to die attach region.
How much chip out/ crack is allowed?

Victor,

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