Cleared it up for me.
Thanks Dave
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of David D. Hillman
Sent: Tuesday, August 11, 2009 9:50 AM
To: [log in to unmask]
Subject: Re: [TN] PCB wetting issue saga, final question
Hello Ioan - There are a number of misconceptions in your email which I'll
try to revise:
(1) The good ole days of fused tin/lead are gone. In general, with a
tin/lead surface finish, you would get solder spread over the entire
surface of a component pad. However, the introduction of the immersion
surface finishes (tin, silver, ENIG) has resulted in a necessary revision
of everyone's wetting expectations. As you described, you are getting good
wetting angles and geometries but just not seeing full pad spread - full
pad spread is not a necessary requirement for a good solder joint. If you
look in the IPC-610 specification in section 5.1, you will find examples
of acceptable solder joints with less that full pad spread. Additionally,
if you are working with an OSP surface finish treatment, it is not unusual
to have less than full pad spread. Many of the HASL finishes act the same
way due to deposit thickness interactions.
(2) The JSTD-003 (and also 002) are specifications have a stated
objective to ".... determine the ability of printed board
conductors.......to wet easily with solder". It would be impossible for
these specifications to include all of the assembly process parameters
used by the electronics industry today. Such a solderability test would be
of no use to the industry as its Gauge R&R would render the test of no
value. The JSTD-003 document lists a specific set of test parameters that
measure the wettability of a printed wiring board so that the user can
understand how that pwb will act in their process. The test flux used in
the 003 specification is a specific formula with a specified amount of
activation - there are a wide range of industry flux formulations that are
much less active and others that are far more aggressive. A standard test
flux is necessary to produce a solderability measure that can be
interpreted by a wide number of process engineers. The test temperature
value is in the same boat - the surface tension of solder is temperature
dependent so a temperature must be specified or we would have a huge range
of answers that would be of little use. The JSTD-003 specification
produces a solderability measure value that the user can use to understand
how the pwb would interact with their set of process parameters. The
purpose of the IPC solderability specifications are not to replicate the
printed wiring assembly process but to produce a measurement of
solderability that the process engineer can then use to determine adequacy
in their process (see section 1.8 Coating Durability of JSTD 003).
(3) The process engineer can always, in coordination/agreement with the
pwb fabricator, use one of the test methods included in the 003
specification that replicates his/her process - see test Method D Wave
solder or test Method E Surface Mount Simulation. The JSTD003
specification has provisions for you to test per your specific process
parameter set if desired.
Hope this helped explain the purpose of the IPC solderability
specifications.
Dave Hillman
JSTD-002 Chairman
[log in to unmask]
Ioan Tempea <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
08/11/2009 07:51 AM
Please respond to
TechNet E-Mail Forum <[log in to unmask]>; Please respond to
Ioan Tempea <[log in to unmask]>
To
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cc
Subject
[TN] PCB wetting issue saga, final question
Hello Technos,
I have been asking questions on Technet about some wetting issues we see
on a particular board and got many useful answers. In the end we've had
the boards tested for solderability by respectable labs and the bare
boards passed J-STD-003 testing with flying colors.
To back track a little bit, the original doubt came from the fact that in
reflow, the solder does wet very well on both the board and the component
in the component pin area, but would stop spreading pretty far from the
land's end. It just stops spreading, even though the wetting angles at the
stop points are very low, so denoting excellent wetting.
And here comes the question: why is testing per J-STD-003 done at 235 C
and with a rather aggressive flux, when the reflow soldering takes place
at 205 C (HASL finish) using a milder flux (I am using WS, but it could
very well be no-clean...)?
Thanks,
Ioan Tempea, ing.
Ingénieur Principal Fabrication / Sr. Manufacturing Engineer
30 ans déjà! - Already 30 years!
950 rue Bergar, Laval, Québec, H7L 5A1
t : 450-967-7100 ext : 244
Mtl : 514-990-5762
f : 450-967-7444
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www.digico.cc <http://www.digico.cc/>
P N'imprimer que si nécessaire - Print only if you must
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