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August 2009

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Subject:
From:
Kenneth Wood <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Kenneth Wood <[log in to unmask]>
Date:
Wed, 19 Aug 2009 16:25:08 -0400
Content-Type:
text/plain
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text/plain (106 lines)
I concur...
I left out our internal design rules from my previous comment but Inge makes
a good point about internal design rules.
Typically, we try to keep copper a minimum of 25mils from the board edges
but 15mil (sometimes lower in extreme cases) is acceptable in close cases.
V-Groove spacing is 45mils from the center of the groove but this is 45mils
with the V-groove we call out. Others may have a different V-groove spec
with 
larger blade offsets and widths so this might not be a good rule for them.
If you want an easy to use version of minimum conductor spacing's then feel
free to download our toolkit...

http://saturnpcb.com/pcb_toolkit.htm

But you need to know the voltages for these traces to properly use the IPC
table 6-1 and since it sounds like a customer of yours designed this PCB,
you may not know the voltages.
So in conclusion you may be better off using the IPC-2222, Table 5-2 chart
that simply defies a keep out area around the V-groove for help.
Hope this helps again...
Ken
_____________________________________
Kenneth J. Wood
Saturn PCB Design, Inc
www.saturnpcb.com


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Inge
Sent: Wednesday, August 19, 2009 4:08 PM
To: [log in to unmask]
Subject: Re: [TN] Minimum Conductor to PCB edge distance

Craig,
You often see conductors extremly close to the edge in order to use as much 
as possible of the area. Understandable but risky. The edges are sensitive 
to touching leading rails, mechanicl damage by handling and cracks in the 
coating etc. Therefore, our guys have decided own rules, hence we have a 
minimum of 1 millimeter as a safety distance for signals and data traces and

5 millimeters for power lines.
Inge

----- Original Message ----- 
From: "Craig Sullivan" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, August 19, 2009 9:34 PM
Subject: [TN] Minimum Conductor to PCB edge distance


I can't seem to find this information in any IPC document, unless I am
obviously overlooking it.

We have a PCB customer designed with a trace close to the board edge
(0.013"). However, when the board is scored for depaneling, the score width
reduces the distance to around 0.005" - 0.007".

Can anyone recommend a reference or design guideline that specifies
something like this? Something that may specify how close features can be
placed to the board edge?

We have our own guidelines for DFA, and generally speaking, we've never run
into anything this tight where it's become a cause for concern. But there's
also a first time I suppose.

Thanks in advance for the input.
Craig

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