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July 2009

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TechNet E-Mail Forum <[log in to unmask]>, Inge <[log in to unmask]>
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Thu, 9 Jul 2009 23:23:01 +0200
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I welcome the answers to these questions, Bev. I have only found issues with 
tests in the range 10,000 to 100,000 temp or switch cyclings (MIL) and how 
many electronic equipments have such requirements. I bought a book, all 
about underfillers and coatings, and it seemed to me as there are lots of 
academic theorizing about the CTE mismatch, but little practical evidence. 
In fact we do some underfilling each time we conformal coat.I've seen large 
BGAs with a lot of coating that has been sucked in because of capillary 
forces. And I have never seen any problem with that. So, the tsunami of 
replies to prove the problem will appear....?
/Inge




TechNetters,
Well I have been shopping to Class 2 people the draft we all built here
on TechNet of a standard for underfill workmanship.  Some are saying
they can't live with voids that only go 50% around the perimeter of a
solder ball, they want more leeway.  They also say they want to allow
voids connecting solder balls.  Now I put in the prohibition of the
latter because of the statement in the J-STD-030 "Guideline for
Selection and Application of Underfill Material for Flip Chip and Other
Micropackages", where it talks about unequal stresses put on the solder
balls when they is not 100 underfill coverage around each and every
ball.  My questions to you are:
1) What is the physical evidence behind that statement in 030?
2) What was the magnitude of the deformation?
3) How long did it take?

My reason for the last question is if it takes 9 years for significant,
reliability impairing deformation to occur in a 20 year life product,
that is real bad.  But if it happens in the products with a 2 to 3 year
life product, why should we care?

Bev
RIM


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