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July 2009

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Subject:
From:
Rex Waygood <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Rex Waygood <[log in to unmask]>
Date:
Mon, 13 Jul 2009 16:52:02 +0100
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I'm interested as to what type of probe you use to make good contact and
ensure you have no risk of damaging the via?
We avoid probing vias at all costs.
The via is a potential reliability concern on a pcb and hitting it
repeatedly with a steel probe doesn't seem sensible.
Regards
Rex

Rex Waygood
Technical Manager
 
Hansatech EMS provides value manufacturing through engineering and
quality
 
Hansatech EMS Limited
Benson Road
Nuffield Industrial Estate
Poole




-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jack Olson
Sent: 10 July 2009 18:20
To: [log in to unmask]
Subject: [TN] ICT and SolderMask

I'm wading into deeper water these days...

(As a circuit board designer,)
We have vias that can be used as test points that are 40mil pads with
13mil holes. Normally we would like mask to cover most of the pad but
not the hole, so we have an 18mil aperture on the mask layer.
Whenever these vias are USED as test points, we have to open up the mask
and leave them fully exposed.

The problem is, no matter how hard we try to generate test point data,
during test fixture development they end up inserting a few more, moving
them around, etc. which means we either have to modify the mask or leave
ALL of them exposed. to minimize the possibility of solder shorts, we
are discussing now to modify the mask instead of leaving them all open,
preferably without having to change the board revision.

Has anyone else had to deal with this situation?

I would be interested to know if you are generating test point data, Is
it really good enough?
Or,
Are they modifying it in production?
If so, do they make an effort to get the TP changes back to you?

the man with the mask,
Jack

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