Jack,
We specify testpoints on schematic and place them just like components. Run
routines to insure that all nets have TPs or are flagged, low ohm resistors
get 2 TPs per side, etc.. Have specific drawing of testpoint placement and
coordinate file. Testability is reviewed before releasing for production,
so nobody tweaks the design but us. We're kinda fanatical about that; we
put boxes where the supplier logos, datecodes, etc. will go.
Regarding solder mask and via holes; first preference for TP is pad only
(pretty hard to achieve on dense design). For via/TP TP side is fully open,
opposite side is as you describe, mask opening just big enough to not fall
in hole.
-Chris
Jack Olson
<[log in to unmask]
M> To
Sent by: TechNet [log in to unmask]
<[log in to unmask]> cc
Subject
07/10/2009 01:20 [TN] ICT and SolderMask
PM
Please respond to
TechNet E-Mail
Forum
<[log in to unmask]>
; Please respond
to
Jack Olson
<[log in to unmask]
M>
I'm wading into deeper water these days...
(As a circuit board designer,)
We have vias that can be used as test points that are 40mil pads
with 13mil holes. Normally we would like mask to cover most of
the pad but not the hole, so we have an 18mil aperture on the
mask layer.
Whenever these vias are USED as test points, we have to open
up the mask and leave them fully exposed.
The problem is, no matter how hard we try to generate test point
data, during test fixture development they end up inserting a few
more, moving them around, etc. which means we either have to
modify the mask or leave ALL of them exposed. to minimize the
possibility of solder shorts, we are discussing now to modify the
mask instead of leaving them all open, preferably without having
to change the board revision.
Has anyone else had to deal with this situation?
I would be interested to know if you are generating test point data,
Is it really good enough?
Or,
Are they modifying it in production?
If so, do they make an effort to get the TP changes back to you?
the man with the mask,
Jack
---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 15.0
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to
[log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16
for additional information, or contact Keach Sasamori at [log in to unmask] or
847-615-7100 ext.2815
-----------------------------------------------------
This e-mail message is intended only for the use of the intended recipient(s).
The information contained therein may be confidential or privileged, and its disclosure or reproduction is strictly prohibited.
If you are not the intended recipient, please return it immediately to its sender at the above address and destroy it.
---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 15.0
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
-----------------------------------------------------
|
