Shawn,



Your culprit is likely the plating topography.  The current carrying (and thermal) constraint is the thinnest area.  If you are paying for 1mil average on a .125 board, even class 3 could go down to 0.787 in the center.

If inner layers are involved, don't forget the making hole conductive (electroless) weak link.



Chris



-----Original Message-----

From: TechNet [mailto:[log in to unmask]] On Behalf Of Upton, Shawn

Sent: Thursday, July 30, 2009 10:49 AM

To: [log in to unmask]

Subject: Re: [TN] Via plating question



I bumped the diameter in the high current area up to 32mil already.  I can't get the 15mil holes to a larger diameter w/o changing the board.  I'll try running with more via's, and larger ones at that, and see what that results in, with just 1mil barrel plating then.  [First board had less copper, no stitching of layers, thermal reliefs on the high current leads, and the board resistance was too high.]



Shawn Upton, KB1CKT

Test Engineer

Allegro MicroSystems, Inc

[log in to unmask]

603.626.2429/fax: 603.641.5336



-----Original Message-----

From: [log in to unmask] [mailto:[log in to unmask]] 

Sent: Thursday, July 30, 2009 10:21 AM

To: [log in to unmask]; Upton, Shawn

Subject: RE: [TN] Via plating question





Shawn, 



You may want to consider simply making the vias a larger diameter,

rather than increasing the plating. If there's room for the larger vias,

I think this would be an easier option.



Regards,



Jason Roetz, CID+

Master Designer 

Eaton Corporation

Electrical Group, Industrial Controls Division

4201 North 27th Street 

Milwaukee, WI. 53216 

Telephone: 414-449-6397

Fax:  414-449-7319

[log in to unmask]

www.eaton.com